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R5F564MFDDFB Datasheet(PDF) 117 Page - Renesas Technology Corp

Part # R5F564MFDDFB
Description  120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory
PDF  228 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F564MFDDFB Datasheet(HTML) 117 Page - Renesas Technology Corp

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R01DS0173EJ0110 Rev.1.10
Page 117 of 228
Oct 24, 2016
RX64M Group
4. I/O Registers
000C 01DCh
ETHER
C0
Carrier Not Detect Counter Register
CNDCR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 01E4h
ETHER
C0
CRC Error Frame Receive Counter Register
CEFCR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 01E8h
ETHER
C0
Frame Receive Error Counter Register
FRECR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 01ECh
ETHER
C0
Too-Short Frame Receive Counter Register
TSFRCR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 01F0h
ETHER
C0
Too-Long Frame Receive Counter Register
TLFRCR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 01F4h
ETHER
C0
Received Alignment Error Frame Counter Register
RFCR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 01F8h
ETHER
C0
Multicast Address Frame Receive Counter Register
MAFCR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 0200h
EDMAC
1
EDMAC Mode Register
EDMR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0208h
EDMAC
1
EDMAC Transmit Request Register
EDTRR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0210h
EDMAC
1
EDMAC Receive Request Register
EDRRR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0218h
EDMAC
1
Transmit Descriptor List Start Address Register
TDLAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0220h
EDMAC
1
Receive Descriptor List Start Address Register
RDLAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0228h
EDMAC
1
ETHERC/EDMAC Status Register
EESR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0230h
EDMAC
1
ETHERC/EDMAC Status Interrupt Enable Register
EESIPR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0238h
EDMAC
1
ETHERC/EDMAC Transmit/Receive Status Copy
Enable Register
TRSCER
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0240h
EDMAC
1
Missed-Frame Counter Register
RMFCR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0248h
EDMAC
1
Transmit FIFO Threshold Register
TFTR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0250h
EDMAC
1
FIFO Depth Register
FDR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0258h
EDMAC
1
Receive Method Control Register
RMCR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0264h
EDMAC
1
Transmit FIFO Underflow Counter
TFUCR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0268h
EDMAC
1
Receive FIFO Overflow Counter
RFOCR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 026Ch
EDMAC
1
Independent Output Signal Setting Register
IOSR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0270h
EDMAC
1
Flow Control Start FIFO Threshold Setting Register
FCFTR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0278h
EDMAC
1
Receive Data Padding Insert Register
RPADIR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 027Ch
EDMAC
1
Transmit Interrupt Setting Register
TRIMD
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 02C8h
EDMAC
1
Receive Buffer Write Address Register
RBWAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 02CCh
EDMAC
1
Receive Descriptor Fetch Address Register
RDFAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 02D4h
EDMAC
1
Transmit Buffer Read Address Register
TBRAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 02D8h
EDMAC
1
Transmit Descriptor Fetch Address Register
TDFAR
32
32
4, 5 PCLKA
2, 3 ICLK
EDMAC
a
000C 0300h
ETHER
C1
ETHERC Mode Register
ECMR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
000C 0308h
ETHER
C1
Receive Frame Length Register
RFLR
32
32
13, 14 PCLKA
2 to 7 ICLK
ETHER
C
Table 4.1
List of I/O Registers (Address Order) (46 / 67)
Address
Module
Symbol Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access Cycles
Related
Function
ICLK
PCLK
ICLK
 PCLK



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