HT56RB688_13 datasheet(74/164 Pages) HOLTEK

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SIMn Control Register 2 - SIMnCTL2 (n=0 or 1) for SPI Mode

Bit

76543210

Name

¾¾

CKPOLn

CKEGn

MLSn

CSENn

WCOLn

TRFn

R/W

¾¾

R/W

POR

¾¾

000000

Bit 7~6

undefined bit, read as 0

Bit 5

CKPOLn: Determines the base condition of the SPI clock line

0: the SCKn line will be high when the SPI clock is inactive

1: the SCKn line will be low when the SPI clock is inactive

The CKPOLn bit determines the base condition of the SPI clock line, if the bit is high, then the

SCKn line will be low when the clock is inactive. When the CKPOLn bit is low, then the SCKn line

will be high when the clock is inactive.

Bit 4

CKEGn: Determines SPI SCKn active clock edge type

CKPOLn=0

0: SCKn is high base level and data capture at SCKn rising edge

1: SCKn is high base level and data capture at SCKn falling edge

CKPOLn=1

0: SCKn is low base level and data capture at SCKn falling edge

1: SCKn is low base level and data capture at SCKn rising edge

The CKEGn and CKPOLn bits are used to setup the way that the clock signal outputs and inputs

data on the SPI bus. These two bits must be configured before data transfer is executed

otherwise an erroneous clock edge may be generated. The CKPOLn bit determines the base

condition of the clock line. If the bit is high, then the SCKn line will be low when the clock is

inactive. When the CKPOLn bit is low, then the SCKn line will be high when the clock is inactive.

The CKEGn bit determines active clock edge type which depends upon the condition of CKPOLn

bit.

Bit 3

MLSn: SPI Data shift order

0: LSB shift first

1: MSB shift first

This is the data shift select bit and is used to select how the data is transferred, either MSB or

LSB first. Setting the bit high will select MSB first and low for LSB first.

Bit 2

CSENn: SPI SCSn pin control

0: Disable

1: Enable

The CSENn bit is used as an enable/disable for the SCSn pin. If this bit is low, then the

SCSn pin will be disabled and placed into a floating condition. If the bit is high the SCSn pin will

be enabled and used as a select pin.

Note that using the CSENn bit can be disabled or enabled via configuration option.

Bit 1

WCOLn: SPI Write Collision flag

0: No collision

1: Collision

The WCOLn flag is used to detect if a data collision has occurred. If this bit is high it means that

data has been attempted to be written to the SIMnDR register during a data transfer operation.

This writing operation will be ignored if data is being transferred. The bit can be cleared by the

application program. Note that using the WCOLn bit can be disabled or enabled via configuration

option.

Bit 0

TRFn: SPI Transmit/Receive Complete flag

0: Data is being transferred

1: SPI data transmission is completed

The TRFn bit is the Transmit/Receive Complete flag and is set to 1 automatically when an SPI

data transmission is completed, but must set to 0 by the application program. It can be used to

generate an interrupt.

Rev. 1.10

April 15, 2013

HT56RB688

TinyPowerTM A/D type Smart Card OTP MCU

with LCD, DAC, ISO 7816 and USB Interfaces

HT56RB688 Datasheet(PDF) 74 Page - Holtek Semiconductor Inc

HT56RB688 Datasheet(HTML) 74 Page - Holtek Semiconductor Inc

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