LAN91C100FD datasheet(26/68 Pages) SMSC

26 / 68 page

SMSC DS – LAN91C100FD REV. B

Page 26

Rev. 05/31/2000

BANK 1

OFFSET

NAME

TYPE

SYMBOL

4 THROUGH 9

INDIVIDUAL ADDRESS REGISTERS

READ/WRITE

IAR

These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or EEPROM reload. The

registers can be modified by the software driver, but a STORE operation will not modify the EEPROM Individual Address

contents. Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable.

LOW

BYTE

ADDRESS 0

HIGH

BYTE

ADDRESS 1

LOW

BYTE

ADDRESS 2

HIGH

BYTE

ADDRESS 3

LOW

BYTE

ADDRESS 4

HIGH

BYTE

ADDRESS 5

BANK 1

OFFSET

NAME

TYPE

SYMBOL

GENERAL PURPOSE REGISTER

READ/WRITE

GPR

HIGH

BYTE

HIGH DATA BYTE

LOW

BYTE

LOW DATA BYTE

This register can be used as a way of storing and retrieving non-volatile information in the EEPROM to be used by the

software driver. The storage is word oriented, and the EEPROM word address to be read or written is specified using the

six lowest bits of the Pointer Register.

This register can also be used to sequentially program the Individual Address area of the EEPROM, that is normally

protected from accidental Store operations.

This register will be used for EEPROM read and write only when the EEPROM SELECT bit in the Control Register is set.

This allows generic EEPROM read and write routines that do not affect the basic setup of the LAN91C100FD.

LAN91C100FD Datasheet(PDF) 26 Page - SMSC Corporation

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