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ELANSC520 Datasheet(PDF) 8 Page - Advanced Micro Devices

Part # ELANSC520
Description  Microcontroller
PDF  440 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

ELANSC520 Datasheet(HTML) 8 Page - Advanced Micro Devices

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Table of Contents
viii
Élan™SC520 Microcontroller Register Set Manual
Slave DMA Channel 3 Memory Address (GPDMA3MAR) . . . . . . . . . . . 11-48
Slave DMA Channel 3 Transfer Count (GPDMA3TC) . . . . . . . . . . . . . . 11-49
Slave DMA Channel 0–3 Status (SLDMASTA). . . . . . . . . . . . . . . . . . . . 11-50
Slave DMA Channel 0–3 Control (SLDMACTL) . . . . . . . . . . . . . . . . . . . 11-51
Slave Software DRQ(n) Request (SLDMASWREQ) . . . . . . . . . . . . . . . 11-53
Slave DMA Channel 0–3 Mask (SLDMAMSK) . . . . . . . . . . . . . . . . . . . . 11-54
Slave DMA Channel 0–3 Mode (SLDMAMODE) . . . . . . . . . . . . . . . . . . 11-55
Slave DMA Clear Byte Pointer (SLDMACBP). . . . . . . . . . . . . . . . . . . . . 11-57
Slave DMA Controller Reset (SLDMARST) . . . . . . . . . . . . . . . . . . . . . . 11-58
Slave DMA Controller Temporary (SLDMATMP) . . . . . . . . . . . . . . . . . . 11-59
Slave DMA Mask Reset (SLDMAMSKRST) . . . . . . . . . . . . . . . . . . . . . . 11-60
Slave DMA General Mask (SLDMAGENMSK) . . . . . . . . . . . . . . . . . . . . 11-61
General 0 (GPDMAGR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-62
Slave DMA Channel 2 Page (GPDMA2PG) . . . . . . . . . . . . . . . . . . . . . . 11-63
Slave DMA Channel 3 Page (GPDMA3PG) . . . . . . . . . . . . . . . . . . . . . . 11-64
Slave DMA Channel 1 Page (GPDMA1PG) . . . . . . . . . . . . . . . . . . . . . . 11-65
General 1 (GPDMAGR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-66
General 2 (GPDMAGR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-67
General 3 (GPDMAGR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-68
Slave DMA Channel 0 Page (GPDMA0PG) . . . . . . . . . . . . . . . . . . . . . . 11-69
General 4 (GPDMAGR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-70
Master DMA Channel 6 Page (GPDMA6PG) . . . . . . . . . . . . . . . . . . . . . 11-71
Master DMA Channel 7 Page (GPDMA7PG) . . . . . . . . . . . . . . . . . . . . . 11-72
Master DMA Channel 5 Page (GPDMA5PG) . . . . . . . . . . . . . . . . . . . . . 11-73
General 5 (GPDMAGR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-74
General 6 (GPDMAGR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-75
General 7 (GPDMAGR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-76
General 8 (GPDMAGR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-77
Master DMA Channel 4 Memory Address (GPDMA4MAR) . . . . . . . . . . 11-78
Master DMA Channel 4 Transfer Count (GPDMA4TC) . . . . . . . . . . . . . 11-79
Master DMA Channel 5 Memory Address (GPDMA5MAR) . . . . . . . . . . 11-80
Master DMA Channel 5 Transfer Count (GPDMA5TC) . . . . . . . . . . . . . 11-81
Master DMA Channel 6 Memory Address (GPDMA6MAR) . . . . . . . . . . 11-82
Master DMA Channel 6 Transfer Count (GPDMA6TC) . . . . . . . . . . . . . 11-83
Master DMA Channel 7 Memory Address (GPDMA7MAR) . . . . . . . . . . 11-84
Master DMA Channel 7 Transfer Count (GPDMA7TC) . . . . . . . . . . . . . 11-85
Master DMA Channel 4–7 Status (MSTDMASTA) . . . . . . . . . . . . . . . . . 11-86
Master DMA Channel 4–7 Control (MSTDMACTL) . . . . . . . . . . . . . . . . 11-87
Master Software DRQ(n) Request (MSTDMASWREQ) . . . . . . . . . . . . . 11-89
Master DMA Channel 4–7 Mask (MSTDMAMSK) . . . . . . . . . . . . . . . . . 11-90
Master DMA Channel 4–7 Mode (MSTDMAMODE) . . . . . . . . . . . . . . . 11-91
Master DMA Clear Byte Pointer (MSTDMACBP) . . . . . . . . . . . . . . . . . . 11-93
Master DMA Controller Reset (MSTDMARST) . . . . . . . . . . . . . . . . . . . 11-94
Master DMA Controller Temporary (MSTDMATMP). . . . . . . . . . . . . . . . 11-95
Master DMA Mask Reset (MSTDMAMSKRST) . . . . . . . . . . . . . . . . . . . 11-96
Master DMA General Mask (MSTDMAGENMSK) . . . . . . . . . . . . . . . . . 11-97
CHAPTER 12
PROGRAMMABLE INTERRUPT CONTROLLER REGISTERS
12-1
12.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
Interrupt Control (PICICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
Master PIC Interrupt Mode (MPICMODE) . . . . . . . . . . . . . . . . . . . . . . . . 12-6
Slave 1 PIC Interrupt Mode (SL1PICMODE) . . . . . . . . . . . . . . . . . . . . . . 12-8
Slave 2 PIC Interrupt Mode (SL2PICMODE) . . . . . . . . . . . . . . . . . . . . . . 12-9
Software Interrupt 16–1 Control (SWINT16_1) . . . . . . . . . . . . . . . . . . . 12-10
Software Interrupt 22–17/NMI Control (SWINT22_17). . . . . . . . . . . . . . 12-13
Interrupt Pin Polarity (INTPINPOL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-15
PCI Host Bridge Interrupt Mapping (PCIHOSTMAP) . . . . . . . . . . . . . . . 12-17
ECC Interrupt Mapping (ECCMAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19



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