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LC823450 Datasheet(PDF) 84 Page - ON Semiconductor |
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LC823450 Datasheet(HTML) 84 Page - ON Semiconductor |
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84 / 112 page ![]() LC823450 www.onsemi.com 84 eMMC Interface Timing • [condition] VDD1 = 0.93 V to 1.27 V, VDDSD0, VDDSD1, VDDSD2 = 1.7 V to 1.95 V or 2.7 V to 3.6 V External load 10 to 40pF Normal(Default) Mode Figure 31. Normal (Default) Mode Clock (from LSI) In put (to LSI) Out put (from LSI) tODLY(max) tODLY(min) t PP t WL t WH t THL t TLH t ISU t IH • [Applied pin] ♦ Clock : SDCLK0, SDCLK1, SDCLK2 ♦ Output : SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] output ♦ Input : SDCMD0, SDCMD1, SDCMD2, SDAT0[3:0], SDAT1[3:0], SDAT2[3:0] input Table 48. I/O Voltage (VDDSD0, VDDSD1, VDDSD2) 2.7 V to 3.6 V 1.7 V to 1.95 V Unit External Load 10 pF to 40 pF 10 pF to 30 pF 10 pF to 23 pF I/O Drivability 8 mA 10 mA 8 mA 6 mA Item Symbol Min Max Min Max Min Max Min Max Clock Frequency fPP 0 26 0 26 0 26 0 26 MHz Clock Low Time tWL 10 − 10 − 10 − 10 − ns Clock High Time tWH 10 − 10 − 10 − 10 − ns Clock Rise Time tTLH − 3 − 3 − 3 − 3 ns Clock Fall Time tTHL − 3 − 3 − 3 − 3 ns Input Set−up Time (from SD to LSI) tISU 6.9 − 8.3 − 8.7 − 10.3 − ns Input Hold−up Time (from SD to LSI) tIH 0.7 − 0 − 0 − 0 − ns Output Delay Time (from LSI to SD) tODLY 3.1 20.1 3.1 20.1 3.1 20.9 3.1 23.2 ns |
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