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LC823450 Datasheet(PDF) 28 Page - ON Semiconductor |
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LC823450 Datasheet(HTML) 28 Page - ON Semiconductor |
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28 / 112 page ![]() LC823450 www.onsemi.com 28 Table 10. TERMINAL FUNCTIONS (continued) Terminal Name Available ( d) IO POWER Function Direction Polarity Multiplexed Function RA XB,XD XA,XC TA IO POWER OTHER, POWER BMODE[1:0] − B Bootmodeselect Vdd2 d d d d TEST Pos I Test mode (normally connect to ground) Vdd2 d d d d NRES Neg I LSI reset Input Vdd2 d d d d Vdd1 − P Digital core power − d 7 d 7 d 7 d 8 Vdd2 − P Digital IO power − d 8 d 8 d 8 d 15 VddSD0 − P Digital IO power (SDI/F Ch0) − d d d d VddSD1 − P Digital IO power (SD(MS)I/F Ch1) − d d d d VddSD2 − P Digital IO power (SDI/F Ch2) − d d d d VddQSPI − P Digital IO power (QSPI) − d 12 d 14 d 14 d 23 Sum 35 37 37 54 All Sum 128 154 154 240 7. This function is not available 8. Set according to the General RTC mode or KeyInt RTC mode. Bonding internally for “TA” product as described on Page 7. 9. SDRAM address bit is 13bit including SDRADDR [12:11]. 10. Set according to the frequency of XT1 (12/20/24/48 MHz). Bonding internally for “TA’’ product as described on Page 5. 11. Audio clock is generated by one of PLL2 (1 V) or PLL3 (3 V). One of PLL2 or PLL3 is available for “TA” and “RA” product. Please refer to Page 5 for more information. Both of PLL2 and PLL3 are available for “XA”,“XB”, “XC” and “XD” products. 12. Audio clock is generated by one of PLL2 (1 V) or PLL3 (3 V). One of PLL2 or PLL3 is available for “TA” and “RA” product. Please refer to Page 5 for more information. Both of PLL2 and PLL3 are available for “XA”,“XB”, “XC” and “XD” products. 13. Analog ground is shared by PLL2 and PLL3. 14. Unused Input terminals and input state terminals of bidirectional should be set Pull−up/Down resister ON or connect to digital power supply or ground (don’t let open). |
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