LC823450 datasheet(88/112 Pages) ONSEMI

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LC823450

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• [applied pin]

♦ Input

: CTS1

♦ Output : TXD1

Table 52.

Item

Condition

Symbol

min

max

unit

Delay Time

Completing preparation to trans-

mit the current TXD data by set-

ting registers at CTS1 = high

From the negative edge

Tdlycts

−

6 T + 20

CTS Setup Time

(not to transmit the next TXD data)

From end of the last StopBit

Tsetupcts

3 T + 20

−

57. T: UART functional clock rate

58. In using hardware flow control by CTS/RTS, if the CTS setup time above is NOT met, the next TXD data will be transmitted at the time of

having prepared it regardless of the CTS level.

RTS Timing

Figure 36. RTS Timing

RTS timing

parity

bit

start

bit

stop

bit1

stop

bit2

parity

bit

start

bit

stop

bit

End of the last Stop Bit

1.5 Bit

Tdlyrts

RXD1

RTS1

• [applied pin]

♦ Input

: RXD1

♦ Output : RTS1

Table 53.

Item

Condition

Symbol

min

max

unit

Delay Time

Receiving the current RXD data with 15 data

existing in Reception FIFO or Receiving the cur-

rent RXD data without using Reception FIFO

From 1.5 Bit before end of the last StopBit

Tdlyrts

−

4 T + 20

59. T: UART functional clock rate

LC823450 Datasheet(PDF) 88 Page - ON Semiconductor

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