LC823450 datasheet(16/112 Pages) ONSEMI

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LC823450

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Table 5. OTHER AREA (CORTEX−M3) (continued)

USB20HC

Cortex−M3−1

DMAC

Address

Cortex−M3−0

Master/Slave

OHCI

EHCI

D−Bus

DMAC

I−Bus

System

− Bus

D−Bus

I−Bus

Address

System

− Bus

Master/Slave

0x4004

0000

OSC System

0x4003

0000

Reserved

0x4002

0000

USB2.0

Device(DMAC)

0x4001

0000

USB2.0

Device(CPU)

0x4000

7000

Reserved

0x4000

6000

DSP CMDIF

0x4000

5000

MUTEX REG

0x4000

4000

DMAC

0x4000

3000

INTC

0x4000

2000

USB2.0 Host

0x4000

1000

S−Flash I/F

0x4000

0000

External MEM CTL

6. Access from internal peripheral bus(AHB/APB).

LPDSP32

Table 6. LPDSP32 − DMA

Address

Master/Slave

LPDSP32

DMA

0x23 7000

Reserved

0x20 0000

220 KB LPDSP32 ROM

0x18 0000

Reserved

0x17 8000

32 KB Internal SRAM (seg 8)

0x14 0000

224 KB Internal SRAM (seg 7)

0x10 0000

256 KB Internal SRAM (seg 6)

0x0C 0000

256 KB Internal SRAM (seg 5)

0x0A 0000

128 KB Internal SRAM (seg 4)

0x08 0000

128 KB Internal SRAM (seg 3)

0x04 0000

256 KB Internal SRAM (seg 2)

0x02 0000

128 KB Internal SRAM (seg 1)

0x00 0000

128 KB Internal SRAM (seg 0)

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