BLUENRG-2 datasheet(54/190 Pages) STMICROELECTRONICS

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Functional details

BlueNRG-2

54/190

DocID030675 Rev 2

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DMA_CH2 peripheral base address (DMA_CH2_BASE_ADDR) 0xA0000030



DMA_CH3 peripheral base address (DMA_CH3_BASE_ADDR) 0xA0000044



DMA_CH4 peripheral base address (DMA_CH4_BASE_ADDR) 0xA0000058



DMA_CH5 peripheral base address (DMA_CH5_BASE_ADDR) 0xA000006C



DMA_CH6 peripheral base address (DMA_CH6_BASE_ADDR) 0xA0000080



DMA_CH7 peripheral base address (DMA_CH7_BASE_ADDR) 0xA0000094

Table 46: DMA_CHx registers

Address

offset

Name

Reset

Description

0x00

CCR

0x00000000

DMA channel configuration register. Refer to the

detailed description below.

0x04

CNDTR

0x00000000

DMA channel number of data register. Refer to the

detailed description below.

0x08

CPAR

0x00000000

DMA channel peripheral address register. Refer to

the detailed description below.

0x0C

CMAR

0x00000000

DMA channel memory address register. Refer to the

detailed description below.

Table 47: DMA_CHx - CCR register description: address offset DMA_CHX_BASE_ADDR+0x00

Bit

Field name

Reset

Description

0x0

DMA channel enable.

0: DMA channel disabled.

1: DMA channel enabled.

TCIE

0x0

Transfer complete interrupt enable.

0: TC interrupt disabled.

1: TC interrupt enabled.

HTIE

0x0

Half transfer interrupt enable.

0: HT interrupt disabled.

1: HT interrupt enabled.

TEIE

0x0

Transfer error interrupt enable.

0: TE interrupt disabled.

1: TE interrupt enabled.

DIR

0x0

Data transfer direction.

0: Read from peripheral.

1: Read from memory.

CIRC

0x0

Circular mode.

0: Circular mode disabled.

1: Circular mode enabled.

PINC

0x0

Peripheral increment mode.

0: Peripheral increment disabled.

1: Peripheral increment enabled.

MINC

0x0

Memory increment mode.

0: Memory increment disabled.

1: Memory increment enabled.

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