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BLUENRG-2 Datasheet(PDF) 55 Page - STMicroelectronics |
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BLUENRG-2 Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 190 page ![]() BlueNRG-2 Functional details DocID030675 Rev 2 55/190 Bit Field name Reset RW Description 9:8 PSIZE 0x0 RW Peripheral size. 00b: Size 8 bits. 01b: Size 16 bits. 10b: Size 32 bits. 11:10 MSIZE 0x0 RW Memory size. 00b: Size 8 bits. 01b: Size 16 bits. 10b: Size 32 bits. 13:12 PL 0x0 RW Channel priority level. 00b: Low priority. 01b: Medium priority. 10b: High priority. 11b: Very high priority. 14 MEM2MEM 0x0 RW Memory to memory mode. 0: Memory to memory mode disabled. 0: Memory to memory mode enabled. 31:15 RESERVED 0x0 R RESERVED Table 48: DMA_CHx - CNDTR register description: address offset DMA_CHX_BASE_ADDR+0x04 Bit Field name Reset RW Description 15:0 NDT 0x0 RW Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 31:16 RESERVED 0x0 R RESERVED Table 49: DMA_CHx - CPAR register description: address offset DMA_CHX_BASE_ADDR+0x08 Bit Field name Reset RW Description |
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