BLUENRG-2 datasheet(93/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

DocID030675 Rev 2

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Table 99: I2C - CR register description: address offset I2CX_BASE_ADDR+0x00

Bit

Field name

Reset

Description

0x0

I²C enable disable:

0: I²C disable.

1: I²C enable.

This bit when deasserted works as software Reset for I²C

peripheral.

2:1

0x0

Select the operating mode:

00b: Slave mode. The peripheral can only respond

(transmit/receive) when addressed by a master device

01b: Master mode. The peripheral works in a multi-master

system where itself cannot be addressed by another master

device. It can only initiate a new transfer as master device.

10b: Master/slave mode. The peripheral works in a multi-

master system where itself can be addressed by another

master device, besides to initiate a transfer as master

device.

SAM

0x0

Slave addressing mode. SAM defines the slave addressing

mode when the peripheral works in slave or master/slave

mode. The received address is compared with the content of

the register SCR.

0: 7-bit addressing mode.

1: 10-bit addressing mode.

5:4

0x0

Speed mode. SM defines the speed mode related to the

serial bit rate:

0: Standard mode (up to 100 K/s).

1: Fast mode (up to 400 K/s).

SGCM

0x0

Slave general call mode defines the operating mode of the

slave controller when a general call is received. This setting

does not affect the hardware general call that is always

managed in transparent mode.

0: transparent mode, the slave receiver recognizes the

general call but any action is taken by the hardware after the

decoding of the message included in the Rx FIFO.

1: direct mode, the slave receiver recognizes the general call

and executes directly (without software intervention) the

related actions. Only the status code word is stored in the

I2C_SR register for notification to the application.

FTX

0x0

FTX flushes the transmit circuitry (FIFO, fsm). The

configuration of the I²C node (register setting) is not affected

by the flushing operation. The flushing operation is

performed on modules working on different clock domains

(system and I²C clocks) and needs several system clock

cycles before being completed. Upon completion, the I²C

node (internal logic) clears this bit. The application must not

access the Tx FIFO during the flushing operation and should

poll on this bit waiting for completion.

0: Flush operation is completed (I2C controller clears the bit).

1: Flush operation is started and in progress (set by

application).

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