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TLE5012B Datasheet(PDF) 10 Page - Infineon Technologies AG |
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TLE5012B Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 50 page ![]() TLE5012B Functional Description Data Sheet 10 Rev. 2.0, 2014-02 2 Functional Description 2.1 Block Diagram Figure 2-1 TLE5012B block diagram 2.2 Functional Block Description 2.2.1 Internal Power Supply The internal stages of the TLE5012B are supplied with several voltage regulators: • GMR Voltage Regulator, VRG • Analog Voltage Regulator, VRA • Digital Voltage Regulator, VRD (derived from VRA) These regulators are directly connected to the supply voltage VDD. 2.2.2 Oscillator and PLL The digital clock of the TLE5012B is given by the Phase-Locked Loop (PLL), which is by default fed by an internal oscillator. In order to synchronize the TLE5012B with other ICs in a system, the TLE5012B can be configured via VRG VRA VRD TLE5012B VDD X GMR Y GMR Temp SD- ADC SD- ADC SD- ADC Digital Signal Processing Unit CORDIC CCU RAM SSC Interface Incremental IF PWM HSM SPC CSQ SCK DATA IFA IFB GND IFC Osc PLL ISM Fuses |
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