PC7410 datasheet(23/54 Pages) ATMEL

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PC7410

2141D–HIREL–02/04

Figure 10. AC Test Load for the 60x Interface

Figure 11 provides the mode select input timing diagram for the PC7410. The mode

select inputs are sampled twice, once before and once after HRESET negation.

Figure 11. Mode Input Timing Diagram

where VM = Midpoint Voltage (OV

DD/2)

L2 Clock AC Specifications

The L2CLK frequency is programmed by the L2 configuration register (L2CR[4:6]) core-

to-L2 divisor ratio. See Table 18 for example core and L2 frequencies at various divi-

sors. Table 12 provides the potential range of L2CLK output AC timing specifications as

defined in Figure 12.

The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then

returned to the L2SYNC_IN input of the PC7410 to synchronize L2CLKOUT at the

SRAM with the processor’s internal clock. L2CLKOUT at the SRAM can be offset for-

ward or backward in time by shortening or lengthening the routing of L2SYNC_OUT to

L2SYNC_IN. See Motorola Application Note AN179/D "PowerPC Backside L2 Timing

Analysis for the PCB Design Engineer."

The minimum L2CLK frequency of Table 12 is specified by the maximum delay of the

internal DLL. The variable-tap DLL introduces up to a full clock period delay in the

L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT signals so that the returning

L2SYNC_IN signal is phase aligned with the next core clock (divided by the L2 divisor

ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this

minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase

aligned with the PC7410 core clock at the SRAMs.

The maximum L2CLK frequency shown in Table 12 is the core frequency divided by

one. Very few L2 SRAM designs will be able to operate in this mode. Most designs will

select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write

access to the L2 SRAMs. The maximum L2CLK frequency for any application of the

PC7410 will be a function of the AC timings of the PC7410, the AC timings for the

SRAM, bus loading and printed circuit board trace length.

Atmel is similarly limited by system constraints and cannot perform tests of the L2 inter-

face on a socketed part on a functional tester at the maximum frequencies of Table 12.

Therefore, functional operation and AC timing information are tested at core-to-L2 divi-

sors of 2 or greater.

Z0 = 50

Ω

RL = 50

Ω

OVDD/2

Output

HRESET

Mode Signals

SYSCLK

First sample

Second sample

PC7410 Datasheet(PDF) 23 Page - ATMEL Corporation

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