GMS77C1001 datasheet(27/44 Pages) HYNIX

27 / 44 page

GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

Otherwise, the previous state of that pin may be read into

the CPU rather than the new state.

When in doubt, it is better to separate these instructions

with a NOP or another instruction not accessing this I/O

port.

FIGURE 10-4 EQUIVALENT CIRCUIT FOR A SINGLE I/O PIN

Name

Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Power-On

Reset

RESET and

WDT Reset

TRIS

N/A

I/O control registers (TRISA, TRISB)

1111 1111

05H

RA3

RA2

RA1

RA0

---- xxxx

---- uuuu

06H

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

TABLE 10-1 SUMMARY OF PORT REGISTERS

Legend: Shaded boxes = unimplemented or unused, - = unimplemented, read as ‘0’, x = unknown, u = unchanged.

Data Bus

Data Reg.

Direction Reg.

Read

VDD

VSS

FIGURE 10-5 SUCCESSIVE I/O OPERATION

output RB

RB7:RB0

Instruction

This example shows a write

fetched

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC+1

PC+2

PC+3

read RB port

no operation

Port pin

written here

Port pin

read here

to RB followed by a read

from RB.

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