GMS77C1001 datasheet(36/44 Pages) HYNIX

36 / 44 page

GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

14.1 Power-On Reset (POR)

The GMS77C100X family incorporates on-chip Power-

On Reset (POR) circuitry which provides an internal chip

reset for most power-up situations. To use this feature, the

user merely ties the RESET/VPP pin to VDD. A simplified

block diagram of the on-chip Power-On Reset circuit is

shown in Figure 14-1.

The Power-On Reset circuit and the Internal Reset Timer

circuit are closely related. On power-up, the reset latch is

set and the IRT is reset. The IRT timer begins counting

once it detects RESET to be high. After the time-out peri-

od, which is typically 7 ms (oscillation stabilization time),

it will reset the reset latch and thus end the on-chip reset

signal.

FIGURE 14-1 SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

VDD

Internal RESET

WDT Time-Overflow

WDT

Power-On

RESET

Power-Fail

Detect

RESET/VPP pin

On-Chip

RC OSC

reset

Internal RESET

Timer ( 8-bit asyn.

ripple counter )

clear

Noise

Filter

FIGURE 14-2 TIME-OUT SEQUENCE ON POWER-UP (RESET NOT TIED TO VDD)

VDD

RESET

INTERNAL POR

IRT TIMER-OUT

INTERNAL RESET

TIRT

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