GMS77C1001 datasheet(43/44 Pages) HYNIX

43 / 44 page

GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

17. TIME-OUT SEQUENCE AND POWER DOWN STATUS BITS (TO/PD)

The TO and PD bits in the STATUS register can be tested

to determine if a RESET condition has been caused by a

power-up condition, a RESET or Watchdog Timer (WDT)

reset, or a RESET or WDT wake-up reset.

These STATUS bits are only affected by events listed in

Table 17-2.

Note: A WDT time-out will occur regardless of the status of

the TO bit. A SLEEP instruction will be executed,

regardless of the status of the PD bit.

Table 14-1 lists the reset conditions for the special function

registers, while Table 14-2 lists the reset conditions for all

the registers.

RESET was caused by

Power-up(POR)

RESET or PFD reset (normal operation)1

1. The TO and PD bits maintain their status (u) until a reset

occurs. A low-pulse on the RESET input does not change the

TO and PD status bits.

RESET Wake-up or PFD reset

(from SLEEP)

WDT reset (normal operation)

WDT wake-up reset (from SLEEP)

TABLE 17-1 TO/PD STATUS AFTER RESET

Event

Remarks

Power-up

WDT Time-out

No effect on PD

SLEEP instruction

CLRWDT instruction

TABLE 17-2 EVENTS AFFECTING TO/PD STATUS

BITS

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