GMS77C1001 datasheet(44/44 Pages) HYNIX

44 / 44 page

GMS77C1000/GMS77C1001

July. 2001 Ver. 1.1

18. POWER FAIL DETECTION PROCESSOR

GMS77C1000X has an on-chip power fail detection cir-

cuitry to immunize against power noise.

If VDD falls below a level for longer 100ns, the power fail

detection processor may reset MCU and preserve the de-

vice from the malfunction due to Power Noise.

The bit6(PFDEN) of OPTION register activates the PFD

Circuit, and bit7(LOWopt) lowers the detection level of

the Power Noise. The normal detection level is typically

3V and the lowered detection level is typically 2.5V. Fig-

ure 18-2 shows a Power Fail Detection Situations where

the detection level is selected by LOWOPT Bit.

Note: The PFD circuit is not implemented on the in circuit

emulator, user can not experiment with it. There

fore, after final development user program, this

function may be experimented on OTP

FIGURE 18-1 POWER FAIL DETECTION PROCESSOR

LOWOPT PFDEN

T0CS

T0SE

PSA

PS2

PS1

PS0

bit7

bit0

321

bit 7

LOWOPT: Power-fail detection level select bit.

1 = Lowered detection level (typ. 2.5V @ 5V)

0 = Normal detection level (typ. 3V @ 5V)

bit 6

PFDEN: Power-fail detection enable bit

1 = Enable power-fail detection

0 = Disable power-fail detection

OPTION

FIGURE 18-2 POWER FAIL DETECTION SITUATIONS

Internal

RESET

VDD

VDD=3V

VDR

TNVDD ≥ 100nS

PFDEN = 1

PFDR

TIRT

Internal

RESET

VDD

VDD=2.5V

VDR

TNVDD ≥ 100nS

PFDR

TIRT

Internal

RESET

VDD

VDD=3/(2.5)V

VDR

PFDR

TIRT

POR

LOWOPT = 0

PFDEN = 1

LOWOPT = 0/1

VDD ≤ VDR

PFDEN = 1

LOWOPT = 1

When VDD falls below approximately 1V level, Power-On Reset may occur.

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