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GMS77C1001 Datasheet(PDF) 29 Page - Hynix Semiconductor

Part # GMS77C1001
Description  8-BIT SINGLE-CHIP MICROCONTROLLERS
PDF  44 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

GMS77C1001 Datasheet(HTML) 29 Page - Hynix Semiconductor

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GMS77C1000/GMS77C1001
26
July. 2001 Ver. 1.1
11.1 Timer Mode
If the OPTION register bit5(T0CS) is cleared, the timer
mode is selected and is operated with internal system clock
(TCY). The Timer0 module will increment every instruc-
tion cycle (without prescaler). If TMR0 register is written,
the increment is inhibited for the following two cycles. The
user can work around this by writing an adjusted value to
the TMR0 register.
Figure 11-3 and Figure 11-4 show the timing diagram of
Timer.
- No Prescaler (PSA=0)
Timer will increment every instruction cycle(Q4).
- With Prescaler (PSA=1)
Timer will increment with prescaler division ratio.
@ PS2~PS0 = (1:2) ~ (1:256)Counter Mode
11.2 Counter Mode
If the OPTION register bit5(T0CS) is set, the counter
mode is selected and operates with event clock input.
In this mode, Timer0 will increment either on every rising
or falling edge of pin EC0. The incrementing edge is deter-
mined by the source edge select bit T0SE (OPTION<4>).
Clearing the T0SE bit selects the rising edge.
FIGURE 11-3 TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
FIGURE 11-4 TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2
[ W ’ TMR0 ]
PC-1
TMR0
Instruction
Fetch
Q1 Q2 Q3 Q4
PC
Q1 Q2 Q3 Q4
PC+1
Q1 Q2 Q3 Q4
PC+2
Q1 Q2 Q3 Q4
PC+3
Q1 Q2 Q3 Q4
PC+4
Q1 Q2 Q3 Q4
PC+5
Q1 Q2 Q3 Q4
PC+6
Q1 Q2 Q3 Q4
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
T0
T0+1
T0+2
NT0
NT0+1
NT0+2
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0+1
Read TMR0
reads NT0+2
PC
(Program
Counter)
Instruction
Executed
increment inhibited
Timer0
Clock
[ W ’ TMR0 ]
PC-1
TMR0
Instruction
Fetch
Q1 Q2 Q3 Q4
PC
Q1 Q2 Q3 Q4
PC+1
Q1 Q2 Q3 Q4
PC+2
Q1 Q2 Q3 Q4
PC+3
Q1 Q2 Q3 Q4
PC+4
Q1 Q2 Q3 Q4
PC+5
Q1 Q2 Q3 Q4
PC+6
Q1 Q2 Q3 Q4
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
[ TMR0 ’ W ]
T0
T0+1
NT0
NT0+1
PC
(Program
Counter)
increment inhabited
Timer0
Clock
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0+1
Read TMR0
reads NT0+2
Instruction
Executed



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