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GMS77C1001 Datasheet(PDF) 35 Page - Hynix Semiconductor |
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GMS77C1001 Datasheet(HTML) 35 Page - Hynix Semiconductor |
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35 / 44 page ![]() GMS77C1000/GMS77C1001 32 July. 2001 Ver. 1.1 14. RESET GMS77C100X devices may be reset in one of the follow- ing ways: - Power-On Reset (POR) - Power-Fail detect reset (PFDR) - RESET (normal operation) - RESET wake-up reset (from SLEEP) - WDT reset (normal operation) - WDT wake-up reset (from SLEEP) Each one of these reset conditions causes the program counter to branch to reset vector address. (GMS77C1000 is 1FFH and GMS77C1001 is 3FFH ). Table 14-1 shows these reset conditions for the PCL and STATUS registers. Some registers are not affected in any reset condition. Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-On Reset (POR), PFDR, RESET or WDT reset. A RESET or WDT wake-up from SLEEP also results in a device reset, and not a continuation of operation before SLEEP. The TO and PD bits (STATUS <4:3>) are set or cleared depending on the different reset conditions. These bits may be used to determine the nature of the reset. Table 14-2 lists a full description of reset states of all reg- isters. Figure 14-1 shows a simplified block diagram of the on-chip reset circuit. Condition PCL Addr: 02H STATUS Addr: 03H Power-On Reset 1111 1111 0001 1xxx RESET reset or PFD reset (normal operation) 1111 1111 000u uuuu1 1. TO and PD bits retain their last value until one of the other reset conditions occur. RESET wake-up or PFD reset (from SLEEP) 1111 1111 0001 0uuu WDT reset (normal operation) 1111 1111 0000 uuuu2 2. The CLRWDT instruction will set the TO and PD bits. Legend : x = unknown, u = unchanged. WDT wake-up (from SLEEP) 1111 1111 0000 0uuu TABLE 14-1 RESET CONDITIONS FOR SPECIAL REGISTERS Register Address Power-On Reset Wake-up Reset RESET, PFDR, WDT Reset WN/A xxxx xxxx uuuu uuuu uuuu uuuu TRIS N/A 1111 1111 1111 1111 1111 1111 OPTION N/A 0011 1111 0011 1111 0011 1111 INDF 00H xxxx xxxx uuuu uuuu uuuu uuuu TMR0 01H xxxx xxxx uuuu uuuu uuuu uuuu PCL1 02H 1111 1111 1111 1111 1111 1111 STATUS1 03H 0001 1xxx 100q quuu 000q quuu FSR 04H 1xxx xxxx 1uuu uuuu 1uuu uuuu PORTA 05H ---- xxxx ---- uuuu ---- uuuu PORTB 06H xxxx xxxx uuuu uuuu uuuu uuuu General Purpose Register Files 07-1FH xxxx xxxx uuuu uuuu uuuu uuuu TABLE 14-2 RESET CONDITIONS FOR ALL REGISTERS 1. See Table 14-1 for reset value for specific conditions. Legend : - = unimplemented, read as ‘0’, x = unknown, u = unchanged. q = see the tables in Section 17 for possible values. |
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