SCD1283 datasheet(23/94 Pages) INTEL

23 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

The CD1283 is a synchronous device. All internal operations occur on edges and levels (phases) of

the internal clock. The internal clock is generated by dividing the external (system) clock by two.

When the CPU performs an I/O cycle with the CD1283, it strobes; address and data are sampled on

the rising edges of the internal clock. As illustrated in Chapter 8.0, external control signals must

meet setup times with respect to system clock edges. Once a cycle starts, the sequence of events is

locked to the CD1283 clock, with events (address setup, write data setup, and read data available)

occurring at predictable times.

It is not necessary to design a synchronous interface to the CD1283. In an asynchronous design, the

DTACK* (Data Transfer Acknowledge) signal indicates that the CD1283 has completed the

requested data transfer for all I/O cycles except DMA. DTACK* can be an input to wait-state

generation logic that pauses the CPU until the operation is complete. If the CS* and DS* strobes

(Chip Select and Data Strobe) do not meet the minimum setup time with respect to the system

clock edge, the CD1283 does not detect the I/O request, and the cycle delays for two full-system

clock cycles, meeting the setup time. The I/O cycle commences and follows the predictable

timing with DTACK* signaling the end.

Figure 2. Functional Block Diagram

Figure 3. Internal Address Generation

BUS

INTERFACE

AND DMA

LOGIC

PARALLEL

PORT FIFO

PARALLEL

PORT LOGIC

CONTROL STATE

MACHINE

INTERRUPT

LOGIC

REGISTERS

PIPELINE

CONTROL

CPU

ADDRESS

GENERATION

AER

RAM REGISTER

ARRAY

PARALLEL PORT

REGISTERS

SCD1283 Datasheet(PDF) 23 Page - Intel Corporation

SCD1283 Datasheet(HTML) 23 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL