SCD1283 datasheet(53/94 Pages) INTEL

53 / 94 page

IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

7.0

Detailed Register Descriptions

This section presents a detailed description of each register. Registers have two formats: full eight

bits, where the entire content defines a single function; or the register is a collection of bits,

grouped singly or in multiples, defining a function. In the second case, the descriptions divide the

the same order as outlined in Chapter 4.0. Bits defined as ‘0’ should not be modified and, if values

other than ‘0’ are read, program execution should not be affected or software compatibility with

future revisions will be uncertain.

7.1

Global Registers

7.1.1

Access Enable Register

The AER provides binary compatibility with the CD1284. Users must program this register with

the least-significant bits set to ‘0’ to access the parallel channel; however, to perform a device reset

through the RCR, AER must = 02h. The contents of the upper 5 bits should be ignored when read.

7.1.2

Global Firmware Revision Code Register

The GFRCR serves two purposes in the CD1283. First, it displays the revision number of the

firmware in the device. When a revision to the CD1283 is required, the revision number of the

firmware is increments by one. The revision code is 24 (hex) for the Revision D device, and 25

(hex) for the Revision E device.

Secondly, this register can be used by the system programmer as an indication of when the internal

processor has completed reset procedures, after either a power-on reset (through the RESET*

input) or a software global reset (through the reset command in the CCR). Immediately after the

reset operation begins, the internal CPU clears the register. When complete, and the CD1283 is

ready to accept host accesses, the register is loaded with the revision code.

Access: R/W

8-Bit Hex Address: 68

Default Value: XX

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

XXX

Access: R/W

8-Bit Hex Address: 4F

Default Value: 25

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Firmware Revision Code

SCD1283 Datasheet(PDF) 53 Page - Intel Corporation

SCD1283 Datasheet(HTML) 53 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL