SCD1283 datasheet(55/94 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

7.1.6

Prescaler Period Register

The PPR sets the divisor used to generate the time period for CD1283 timer operations. It can be

set to any value between 0 and 255 (x’FF). The PPR is clocked by the system clock prescaled

(divided) by 512. For best device operation, the value loaded into the PPR should not be less than

x’30.

7.1.7

Service Request Register

The SVRR reflects the inverse of the state of the service request pins (DMAREQ* and

SVCREQP*). Its primary use is in polled systems, and it allows system software to determine

what, if any, service requests are pending

Bit

Description

PPireq: Internal logic sets this bit to generate the external service request output. It is a direct reflection of

the inverse state of the SVCREQP* pin; it is the active-high output of the latch that drives the SVCREQP*

pin. This bit can be scanned by the host to detect an active service request. This bit is cleared by the internal

logic at the beginning of the hardware service-acknowledge cycle or by toggling InTen (PFCR[4]). Clearing

PIR automatically deactivates the SVCREQP* output and clears the SRP bit (SVRR[3]).

6:5

PPort and Pipeline: These two bits indicate which of the two functional blocks of the parallel port are

requesting service. When PPort is set, it indicates that the parallel channel control state machine is the

cause of the request; when Pipeline is set, it indicates that the data pipeline is requesting service. If both bits

are set, it indicates that both blocks are requesting service simultaneously.

4:0

Reserved: The remainder of the bits in the PIR always return ‘0’ when read by the host and should not be

modified.

Access: R/W

8-Bit Hex Address: 7E

Default Value: FF

Bit 7

Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Binary Value

Access: Read only

8-Bit Hex Address: 67

Default Value: 00

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DMAREQ

XSRP

Bit

Description

DMA Request Status: When this bit is set to ‘1’, it indicates that a request is pending.

6:4

These bits are not used and are don’t cares.

Service Request Parallel: When this bit is set to ‘1’, it indicates that a request is pending.

2:0

These bits are not used and are don’t cares.

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