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NT5CC128M8GP-DHT Datasheet(PDF) 72 Page - Nanya Technology Corporation. |
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NT5CC128M8GP-DHT Datasheet(HTML) 72 Page - Nanya Technology Corporation. |
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72 / 160 page  Version 2.2 72 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Timing Parameters In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max. Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance. Maximum RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from ODTLoff. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered low. Synchronous ODT Timing Example for AL=3; CWL=5; ODTLon=AL+CWL-2=6; ODTLoff=AL+CWL-2=6 Synchronous ODT example with BL=4, WL=7 ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BL=4) or ODTH8 (BL=8) after Write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of Write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the Write command at T7. CK CK AL=3 T11 T10 T0 T1 T3 T5 T6 T7 T9 T2 T4 T8 T12 ODT ODTH4, min ODTLon = CWL + AL -2 ODTLoff = CWL + AL -2 T13 T14 T15 CWL - 2 DRAM_RTT tAONmin tAONmax tAONmin tAONmax RTT_NOM AL=3 Transitioning Do not care CKE CK CK ODTH4 T11 T10 T0 T1 T3 T5 T6 T7 T9 T2 T4 T8 T12 ODT ODTLon = CWL -2 T13 T14 T15 ODTLoff = WL - 2 DRAM_RTT tAONmin tAONmax tAOFmax RTT_NOM T16 T17 T18 ODTH4min ODTH4 ODTLoff = CWL -2 ODTLon = CWL -2 tAOFmin tAOFmax tAONmax tAONmin tAOFmin NOP NOP NOP NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Transitioning Do not care |
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