NT5CC128M8GP-DHT datasheet(33/160 Pages) NANYA

33 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

No Operation (NOP) Command

The No operation (NOP) command is used to instruct the selected DDR3(L) SDRAM to perform a NOP (

low and RA,

A, and WE high). This prevents unwanted commands from being registered during idle or wait states. Operations

already in progress are not affected.

Deselect Command

The DESELECT function (

HIGH) prevents new commands from being executed by the DDR3(L) SDRAM. The DDR3(L)

SDRAM is effectively deselected. Operations already in progress are not affected.

DLL- Off Mode

DDR3(L) DLL-

off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until A0

t set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.

The DLL-off Mode operations listed below are an optional feature for DDR3(L). The maximum clock frequency for DLL-off

Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the

refresh interval, tREFI.

Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency (CWL)

in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6.

DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data

relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain.

Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command,

the DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not be

small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and tDQSCKmax is

significantly larger than in DLL-on mode.

The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)

NT5CC128M8GP-DHT Datasheet(PDF) 33 Page - Nanya Technology Corporation.