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NT5CC128M8GP-DHT Datasheet(PDF) 76 Page - Nanya Technology Corporation. |
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NT5CC128M8GP-DHT Datasheet(HTML) 76 Page - Nanya Technology Corporation. |
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76 / 160 page ![]() Version 2.2 76 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP ODT Timing Diagrams Dynamic ODT: Behavior with ODT being asserted before and after the write Note: Example for BC4 (via MRS or OTF), AL=0, CWL=5. ODTH4 applies to first registering ODT high and to the registration of the Write command. In this example ODTH4 would be satisfied if ODT went low at T8. (4 clocks after the Write command). Dynamic ODT: Behavior without write command, AL=0, CWL=5 Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. CK CK T11 T10 T0 T1 T3 T5 T6 T7 T9 T2 T4 T8 T12 T13 T14 T15 T16 CMD ODT RTT DQS/DQS DQ ODTLon ODTLcwn4 T17 ODTLcnw tAONmin tAONmax tADCmin tADCmax WL tADCmin tADCmax tAOFmin tAOFmax Address RTT_WR Din n Din n+1 Din n+2 Din n+3 ODTH4 ODTLoff NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Valid ODTH4 RTT_Nom Do not care Transitioning RTT_Nom tADCmax CK CK T11 T10 T0 T1 T3 T5 T6 T7 T9 T2 T4 T8 CMD ODT RTT DQS/DQS DQ ODTLon ODTLoff tAONmin tAONmax tADCmin RTT_Nom Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Address ODTH4 ODTLoff Do not care Transitioning |
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