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NT5CC128M8GP-DHT Datasheet(PDF) 24 Page - Nanya Technology Corporation. |
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NT5CC128M8GP-DHT Datasheet(HTML) 24 Page - Nanya Technology Corporation. |
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24 / 160 page  Version 2.2 24 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Mode Register MR2 The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write latency. The Mode Register 2 is written by asserting low on , RA, A, WE high on BA1 and low on BA0 and BA2, while controlling the states of address pins according to the table below. MR2 Definition BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 0 0 SRT ASR A6 A2 A1 A0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 0 0 A10 A9 1 0 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 A5 A4 A3 0 0 0 A7 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 BA1 BA0 1 1 1 0 0 0 1 1 0 1 1 Quarter Array (BA[2:0]=110, &111) 1/8th Array (BA[2:0]=111) PASR Full Array HalfArray (BA[2:0]=000,001,010, &011) Quarter Array (BA[2:0]=000, & 001) 1/8th Array (BA[2:0] = 000) 3/4 Array (BA[2:0] = 010,011,100,101,110, & 111) HalfArray (BA[2:0] = 100, 101, 110, &111) MR select 0 Rtt_WR CWL PASR RFU CWL 7 (1.875ns>=tCK(avg)>=1.5ns) 8 (1.5ns>=tCK(avg)>=1.25ns) 9 (1.25ns>=tCK(avg)>=1.07ns) ASR Manual SR Reference (SRT) ASR enable Rtt_WR Dynamic ODT off RZQ/4 RZQ/2 Reserved 6 (2.5ns>=tCK(avg)>=1.875ns) SRT MR select MR0 10 (1.07ns>=tCK(avg)>=0.935ns) RFU 5 (tCK(avg)>=2.5ns) MR1 MR2 MR3 Normal operating temperature range Extended operating temperature range 0 1 * 1 : Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand. * 2 : BA2, A5, A8, A11 ~ A13 are RFU and must be programmed to 0 during MRS. * 3 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled. During write leveling, Dynamic ODT is not available. |
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