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NT5CC128M8GP-DHT Datasheet(PDF) 29 Page - Nanya Technology Corporation. |
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NT5CC128M8GP-DHT Datasheet(HTML) 29 Page - Nanya Technology Corporation. |
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29 / 160 page ![]() Version 2.2 29 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP MPR MR3 Register Definition MR3 A[2] MR3 A[1:0] Function Burst Length Read Address A[2:0] Burst Order and Data Pattern 1b 00b Read Predefined Pattern for System Calibration BL8 000b Burst order 0,1,2,3,4,5,6,7 Pre-defined Data Pattern [0,1,0,1,0,1,0,1] BC4 000b Burst order 0,1,2,3 Pre-defined Data Pattern [0,1,0,1] BC4 100b Burst order 4,5,6,7 Pre-defined Data Pattern [0,1,0,1] 1b 01b RFU BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 1b 10b RFU BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 1b 11b RFU BL8 000b Burst order 0,1,2,3,4,5,6,7 BC4 000b Burst order 0,1,2,3 BC4 100b Burst order 4,5,6,7 NOTE: Burst order bit 0 is assigned to LSB and the burst order bit 7 is assigned to MSB of the selected MPR agent. |
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