 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
NT5CC128M8GP-DHT Datasheet(PDF) 22 Page - Nanya Technology Corporation. |
|
|
|||||||||||||||||||||||||||||
NT5CC128M8GP-DHT Datasheet(HTML) 22 Page - Nanya Technology Corporation. |
|
|
22 / 160 page  Version 2.2 22 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Additive Latency (AL) Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in DDR3(L) SDRAM. In this operation, the DDR3(L) SDRAM allows a read or write command (either with or without auto-precharge) to be issued immediately after the active command. The command is held for the time of the Additive Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency (CWL) register settings. A summary of the AL register options are shown as the following table. Additive Latency (AL) Settings A4 A3 AL 0 0 0, (AL Disable) 0 1 CL-1 1 0 CL-2 1 1 Reserved |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
