GS3471 datasheet(35/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

35 of 179

Semtech

www.semtech.com

4.11.5.1 Delay Line

The GS3471 has the ability to shift the Setup/Hold window on the receive interface, by

using an on-chip delay line to shift the phase of PCLK with respect to the data bus. The

timing of the PCLK output, relative to the data, can be adjusted through the host

interface registers. Each data rate has its own 5-bit delay line offset setting as well as a

PCLK invert option.

The delay adjustment range is defined in Table 4-7. The PCLK output can be delayed by

up to 0.5UI using the rate dependent PCLK_DELAY_XX parameters and it can be

advanced by 0.5UI by using the PCLK_INVERT_XX parameters.

4.11.6 DDR Parallel Clock Timing

The GS3471 has the ability to transmit 10-bit parallel video data with a DDR (Dual Data

Rate) pixel clock over a single-ended interface.

The default DDR timing is configured such that a rising clock edge can be used by a

downstream device to clock in data from the C Stream (SD and HD) and Data Stream 2

(3G), and the falling clock edge can be used by a receiving device to clock in data from

the Y Stream (SD and HD) and Data Stream 1 (3G).

Figure 4-6: DDR Video Interface - 3G Level A

Table 4-7: Delay Adjustment Range

Data Rate

Delay Line Control Parameter

Delay Range (UI)

PCLK_DELAY_SD[14:10]

0.1

PCLK_DELAY_HD[9:5]

0.5

PCLK_DELAY_3G[4:0]

0.5

Cb1

Cr1

Cb2

Cr2

Cb3

Cr3

Cb4

Cr4

20-bit bus

(transition rate = 74.25MHz)

Cb0

Cb1

Cb2

Cb3

Cb4

Cr0

Cr1

Cr2

Cr3

Cr4

PCLK

(148.5MHz)

Cb0

Cr0

10-bit bus

(transition rate = 148.5MHz)

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