GS3471 datasheet(28/179 Pages) SEMTECH

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GS3471

Final Data Sheet Rev.4

PDS-060498

September 2017

28 of 179

Semtech

www.semtech.com

Figure 4-5: EQ_STAT Output MUXing

4.4 Modes of Operation

4.4.1 Auto and Manual Mode

The lock detection algorithm is a continuous process, beginning at device power-up or

after a system reset. It continues until the device is powered down or held in reset.

The device first determines if a valid serial digital input signal has been presented to the

device. If no valid serial data stream has been detected, the serial data into the device is

considered invalid, and the LOCKED signal is LOW.

Once a valid input signal has been detected, the device attempts to detect the presence

of either TRS words or DVB-ASI sync words.

By default, the device powers up in Auto mode (the AUTO_MAN bit in the host interface

is set HIGH). In this mode, the device operating frequency toggles between 3G, HD, and

SD rates as it attempts to lock to the incoming data rate. As it searches through rates,

PCLK output cycles through 148.5MHz, 74.25MHz, 27MHz, and 13.5MHz. The PCLK

output pin can be set to be high-impedance when not locked through GSPI.

When the device is operating in Manual mode (AUTO_MAN bit in the host interface

bits in the host interface. RATE_SEL_TOP[0] = SD/HD and RATE_SEL_TOP[1] = 3G/HD.

Note: The SD/HD bit takes precedence over the 3G/HD bit, so if the SD/HD bit is HIGH,

the 3G/HD bit is ignored.

CARRIER DETECT (SD)

Reserved

CARRIER DETECT

CARRIER DETECT (HD)

CARRIER DETECT (3G)

Reserved

INT_CD_MODE_SEL

AFE_RD_CD_MUX_OUT

EQ_LOS

Reserved

Rate Change Detected

Reserved

CARRIER DETECT and Rate Detect (for any rates

selected with DATA_RATE_DETECTION)

CARRIER DETECT and Rate Detect (for any rates

selected with DATA_RATE_DETECTION with an eight

40MHz pulse low when rate changes)

INT_SOURCE_SEL

EQ_STAT

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