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GS3471 Datasheet(PDF) 4 Page - Semtech Corporation

Part # GS3471
Description  3G, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
PDF  179 Pages
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS3471 Datasheet(HTML) 4 Page - Semtech Corporation

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GS3471
Final Data Sheet Rev.4
PDS-060498
September 2017
4 of 179
Semtech
www.semtech.com
Contents
1. Pin Out .................................................................................................................................................................7
1.1 Pin Assignment ...................................................................................................................................7
1.2 Pin Descriptions ..................................................................................................................................7
2. Electrical Characteristics............................................................................................................................. 11
2.1 Absolute Maximum Ratings ........................................................................................................ 11
2.2 Recommended Operating Conditions .................................................................................... 11
2.3 DC Electrical Characteristics ........................................................................................................ 12
2.4 AC Electrical Characteristics ......................................................................................................... 14
3. Input/Output Circuits.................................................................................................................................. 18
4. Detailed Description.................................................................................................................................... 21
4.1 Functional Overview ...................................................................................................................... 21
4.2 Device Power-Up ............................................................................................................................. 23
4.2.1 Power-Down Mode............................................................................................................. 23
4.2.2 Device Reset .......................................................................................................................... 25
4.3 Automatic (Adaptive) Cable Equalization .............................................................................. 25
4.3.1 Cable Length Indication.................................................................................................... 25
4.3.2 Programmable Squelch Threshold ............................................................................... 26
4.3.3 Equalizer Loss of Signal (EQ LOS) .................................................................................. 26
4.4 Modes of Operation ........................................................................................................................ 28
4.4.1 Auto and Manual Mode .................................................................................................... 28
4.4.2 Low Latency Video Path....................................................................................................29
4.4.3 SMPTE and SMPTE Bypass Mode ................................................................................... 29
4.4.4 DVB-ASI Mode ...................................................................................................................... 30
4.5 Digital Differential Input (DDI/DDI) ........................................................................................... 30
4.6 Serial Digital Input (SDI/SDI) ........................................................................................................ 30
4.6.1 Upstream Launch Swing Compensation .................................................................... 30
4.7 Serial Digital Loop-Through Output .........................................................................................30
4.8 Serial Digital Retimer ...................................................................................................................... 31
4.9 External Crystal/Reference Clock ............................................................................................... 31
4.10 Lock Detect ...................................................................................................................................... 32
4.11 Parallel Data Outputs ................................................................................................................... 32
4.11.1 Parallel Data Bus Output Levels................................................................................... 32
4.11.2 Parallel Output in SMPTE Mode................................................................................... 32
4.11.3 Parallel Output in DVB-ASI Mode................................................................................ 33
4.11.4 Parallel Output in Data-Through Mode .................................................................... 33
4.11.5 Parallel Output Data Format Clock/PCLK Settings ............................................... 33
4.11.6 DDR Parallel Clock Timing ............................................................................................. 35
4.12 Timing Signal Extraction ............................................................................................................ 37
4.12.1 Automatic Switch Line Lock Handling ...................................................................... 37
4.12.2 Manual Switch Line Lock Handling ............................................................................ 38
4.13 Programmable Multi-Function Outputs ............................................................................... 39
4.14 H:V:F Timing Signal Extraction ................................................................................................. 40
4.14.1 CEA-861 Timing Generation ......................................................................................... 42



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