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GS3471 Datasheet(PDF) 103 Page - Semtech Corporation |
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GS3471 Datasheet(HTML) 103 Page - Semtech Corporation |
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103 / 179 page ![]() GS3471 Final Data Sheet Rev.4 PDS-060498 September 2017 103 of 179 Semtech www.semtech.com 4.23 JTAG Test Operation When the JTAG_EN/DIS pin of the GS3471 is set HIGH, test mode is enabled. The JTAG can be used as a stand-alone in-circuit ATE (Automatic Test Equipment) during PCB assembly. When the JTAG tests are applied by ATE, care must be taken to disable any other devices driving the digital I/O pins. If the tests are to be applied only at ATE, this can be accomplished with tri-state buffers used in conjunction with the JTAG_EN/DIS input signal. This is shown in Figure . Scan coverage is limited to digital pins only. There is no scan coverage for analog pins DDO/DDO, RBIAS, LF, CT0, and CT1. The JTAG_EN/DIS pin must be held LOW during scan and therefore has no scan coverage. Please contact your Semtech representative to obtain the BSDL model for the GS3471. |
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