TI-'HYLFHŒ

GND

BIAS

IN

EN

NR/SS

OUT

PG

FB

To Load

Input

Supply

Optional Bias

Supply

21

TPS7A52

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SBVS295 – NOVEMBER 2019

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8.2 Typical Application

This section discusses the implementation of the TPS7A52 using an adjustable feedback network to regulate a

4-A load requiring good PSRR at high frequency with low-noise at an output voltage of 0.9 V. Figure 9 provides a

schematic for this typical application circuit.

Figure 9. Typical Application for a 0.9-V Rail

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 6 as the input parameters.

Table 6. Design Parameters

PARAMETER

DESIGN REQUIREMENT

Input voltage

1.2 V, ±3%, provided by the dc/dc converter switching at 500 kHz

Bias voltage

5V, ±5%

Output voltage

0.9 V, ±1%

Output current

4.0 A (maximum), 100 mA (minimum)

RMS noise, 10 Hz to 100 kHz

PSRR at 500 kHz

> 40 dB

Start-up time

< 25 ms

8.2.2 Detailed Design Procedure

300-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high

temperature on some devices, the TPS7A52 can enter dropout if both the input and output supply are beyond

the edges of the respective accuracy specification.

For a 0.9-V output. use external adjustable resistors. See the resistor values in listed Table 5 for choosing

resistors for a 0.9 V output.

Input and output capacitors are selected in accordance with the Recommended Capacitor Types section.

Ceramic capacitances of 47 µF for the input and one 47-µF capacitor in parallel with two 10-µF capacitors for the

output are selected.

Equation 9 calculates this value.

(9)

At the 4.0-A maximum load, the internal power dissipation is 1.2 W and corresponds to a 52°C junction

temperature rise for the RPS package on a standard JEDEC board. With a 55°C maximum ambient temperature,

selected.