TPS7A5201RPST datasheet(5/28 Pages) TI1

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TPS7A52

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SBVS295 – NOVEMBER 2019

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(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2)

JEDEC standard.

(3)

EVM model.

6.4 Thermal Information

THERMAL METRIC(1)

TPS7A54

UNIT

RPS (VQFN)(2)

RPS (VQFN)(3)

12 PINS

RθJA

Junction-to-ambient thermal resistance

68.7

46.5

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

43.8

°C/W

RθJB

Junction-to-board thermal resistance

19.3

N/A

°C/W

ΨJT

Junction-to-top characterization parameter

1.3

4.5

°C/W

ΨJB

Junction-to-board characterization parameter

18.9

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

4.2

11.4

°C/W

(1)

VOUT(nom) is the calculated VOUT target value from the ANY-OUT in a fixed configuration. In an adjustable configuration, VOUT(nom) is the

expected VOUT value set by the external feedback resistors.

6.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to +125°C), VIN = 1.4 V or VIN = VOUT(nom) + 0.5 V (whichever is

greater), VBIAS = open, VOUT(nom) = 0.8 V

(1), OUT connected to 50 Ω to GND, V

EN = 1.1 V, CIN = 10 µF, COUT = 47 µF, CNR/SS =

0 nF, CFF = 0 nF, and PG pin pulled up to VIN with 100 kΩ (unless otherwise noted); typical values are at TJ = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VFB

Feedback voltage

0.8

VNR/SS

NR/SS pin voltage

0.8

VUVLO+(IN)

Rising input supply

UVLO with BIAS

VIN rising with VBIAS = 3 V

1.02

1.085

VUVLO-(IN)

Falling input supply

UVLO with BIAS

VIN falling with VBIAS = 3 V

0.55

0.7

VUVLO+(IN)

Rising input supply

UVLO without BIAS

VIN rising

1.31

1.39

VUVLO-(IN)

Falling input supply

UVLO without BIAS

VIN falling

0.65

1.057

VUVLO+(BIAS)

Rising bias supply

UVLO

VBIAS rising, VIN = 1.1 V

2.83

2.9

VUVLO-(BIAS)

Falling bias supply

UVLO

VBIAS falling, VIN = 1.1 V

2.45

2.54

VOUT

Output voltage range

0.8

5.2

VOUT

Output voltage

accuracy

1.4 V

≤ VIN ≤ 6.5 V,

0.8 V

≤ VOUT ≤ 5.2 V,

5 mA

≤ IOUT ≤ 2 A

–0.75

0.75

VIN =1.1 V,

5 mA

≤ IOUT ≤ 2 A,

3 V

≤ VBIAS ≤ 6.5 V

–0.75

0.75

DVOUT/ΔVIN

Line regulation

IOUT = 5 mA,

1.4 V

≤ VIN ≤ 6.5 V

0.03

mV/V

DVOUT/ΔVIN

Load regulation

5 mA

≤ IOUT ≤ 4 A,

3 V

≤ VBIAS ≤ 6.5 V,

VIN = 1.1 V

0.07

mV/A

5 mA

≤ IOUT ≤ 4 A

0.012

VOS

Error amplifier offset

voltage

VIN = 1.4 V;

IOUT = 5mA;

-40

℃ ≤ TJ ≤ +125℃

–2

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