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WM8960CGEFL/V Datasheet(PDF) 64 Page - Cirrus Logic

Part # WM8960CGEFL/V
Description  Speaker and Headphone Drivers for Portable Audio Applications
PDF  94 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8960CGEFL/V Datasheet(HTML) 64 Page - Cirrus Logic

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WM8960
64
Rev 4.4
Example:
MCLK=12MHz, required clock = 12.288MHz.
R should be chosen to ensure 5 < PLLN < 13. There is a fixed divide by 4 in the PLL and a selectable
divide by N after the PLL which should be set to divide by 2 to meet this requirement.
Enabling the divide by 2 sets the required f2 = 4 x 2 x 12.288MHz = 98.304MHz.
R = 98.304 / 12 = 8.192
PLLN = int R = 8
k = int ( 224 x (8.192
– 8)) = 3221225 = 3126E9h
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R52 (34h)
PLL N value
4
PLLPRESCALE
0
Divide MCLK by 2 before input to
PLL
0 = Divide by 1
1 = Divide by 2
3:0
PLLN
8h
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
R53 (35h)
PLL K value
(1)
5:0
PLLK [23:16]
31h
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
R54 (36h)
PLL K Value
(2)
8:0
PLLK [15:8]
26h
R55 (37h)
PLL K Value
(3)
8:0
PLLK [7:0]
E9h
Table 44 PLL Frequency Ratio Control
The PLL performs best when f2 is between 90MHz and 100MHz. Its stability peaks at N=8. Some
example settings are shown in Table 45.
MCLK
(MHz)
(f1)
DESIRED OUTPUT
(SYSCLK)
(MHz)
f2
(MHz)
R
N
K
12
11.2896
90.3168
1
2
4
7.5264
7h
86C226h
12
12.288
98.304
1
2
4
8.192
8h
3126E8h
13
11.2896
90.3168
1
2
4
6.947446
6h
F28BD4h
13
12.288
98.304
1
2
4
7.561846
7h
8FD525h
14.4
11.2896
90.3168
1
2
4
6.272
6h
45A1CAh
14.4
12.288
98.304
1
2
4
6.826667
6h
D3A06Eh
19.2
11.2896
90.3168
2
2
4
9.408
9h
6872AFh
19.2
12.288
98.304
2
2
4
10.24
Ah
3D70A3h
19.68
11.2896
90.3168
2
2
4
9.178537
9h
2DB492h
19.68
12.288
98.304
2
2
4
9.990243
9h
FD809Fh
19.8
11.2896
90.3168
2
2
4
9.122909
9h
1F76F7h
19.8
12.288
98.304
2
2
4
9.929697
9h
EE009Eh
24
11.2896
90.3168
2
2
4
7.5264
7h
86C226h



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