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WM8960CGEFL/V Datasheet(PDF) 83 Page - Cirrus Logic |
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WM8960CGEFL/V Datasheet(HTML) 83 Page - Cirrus Logic |
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83 / 94 page ![]() WM8960 Rev 4.4 83 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 3:1 RIN2BOOST[2:0] 000 RINPUT2 to Boost Mixer Gain 000 = Mute 001 = -12dB ...3dB steps up to 111 = +6dB Input Signal Path 0 0 Reserved R45 (2Dh) Left Bypass 8 0 Reserved 7 LB2LO 0 Left Input Boost Mixer to Left Output Mixer 0 = Disable (Mute) 1 = Enable Path Output Signal Path 6:4 LB2LOVOL[2:0] 101 Left Input Boost Mixer to Left Output Mixer Volume 000 = 0dB ...(3dB steps) 111 = -21dB Output Signal Path 3:0 0000 Reserved R46 (2Eh) Right Bypass 8 0 Reserved 7 RB2RO 0 Right Input Boost Mixer to Right Output Mixer 0 = Disable (Mute) 1 = Enable Path Output Signal Path 6:4 RB2ROVOL[2:0] 101 Right Input Boost Mixer to Right Output Mixer Volume 000 = 0dB ...(3dB steps) 111 = -21dB Output Signal Path 3:0 0000 Reserved R47 (2Fh) Power Mgmt (3) 8:6 000 Reserved 5 LMIC 0 Left Channel Input PGA Enable 0 = PGA disabled 1 = PGA enabled (if AINL = 1) Input Signal Path 4 RMIC 0 Right Channel Input PGA Enable 0 = PGA disabled 1 = PGA enabled (if AINR = 1) Input Signal Path 3 LOMIX 0 Left Output Mixer Enable Control 0 = Disabled 1 = Enabled Output Signal Path 2 ROMIX 0 Right Output Mixer Enable Control 0 = Disabled 1 = Enabled Output Signal Path 1:0 00 Reserved R48 (30h) Additional Control (4) 8 0 Reserved 7 GPIOPOL 0 GPIO Polarity Invert 0 = Non inverted 1 = Inverted General Purpose Input / Output 6:4 GPIOSEL[2:0] 000 ADCLRC/GPIO1 GPIO Function Select: 000 = Jack detect input 001 = Reserved 010 = Temperature ok 011 = Debounced jack detect output 100 = SYSCLK output 101 = PLL lock 110 = Logic 0 111 = Logic 1 General Purpose Input / Output |
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