WM8960CGEFLSLASHV datasheet(67/94 Pages) CIRRUS

67 / 94 page

WM8960

Rev 4.4

POWER MANAGEMENT

The WM8960 has three control registers that allow users to select which functions are active. For

minimum power consumption, unused functions should be disabled. To avoid any pop or click noise, it

is important to enable or disable functions in the correct order (see

“Applications Information”).

VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a

2x50k

 potential divider or, for low power maintenance of Vref when all other blocks are disabled, as

a 2x250k

 potential divider.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R25 (19h)

Power

Management

(1)

8:7

VMIDSEL

Vmid Divider Enable and Select

00 = Vmid disabled (for OFF mode)

01 = 2 x 50k

 divider enabled (for playback /

record)

10 = 2 x 250k

 divider enabled (for low-

power standby)

11 = 2 x 5k

 divider enabled (for fast start-

up)

VREF

VREF (necessary for all other functions)

0 = Power down

1 = Power up

AINL

Analogue Input PGA and Boost Left

0 = Power down

1 = Power up

(Note: LMIC must also be set to enable the

PGA)

AINR

Analogue Input PGA and Boost Right

0 = Power down

1 = Power up

(Note: RMIC must also be set to enable the

PGA)

ADCL

ADC Left

0 = Power down

1 = Power up

ADCR

ADC Right

0 = Power down

1 = Power up

MICB

MICBIAS

0 = Power down

1 = Power up

DIGENB

Master Clock Disable

0 = Master clock enabled

1 = Master clock disabled

WM8960CGEFL/V Datasheet(PDF) 67 Page - Cirrus Logic

WM8960CGEFL/V Datasheet(HTML) 67 Page - Cirrus Logic

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