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WM8960CGEFL/V Datasheet(PDF) 79 Page - Cirrus Logic |
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WM8960CGEFL/V Datasheet(HTML) 79 Page - Cirrus Logic |
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79 / 94 page ![]() WM8960 Rev 4.4 79 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION REFER TO 0 DIGENB 0 Master Clock Disable 0 = Master clock enabled 1 = Master clock disabled Power Management R26 (1Ah) Power Mgmt (2) 8 DACL 0 DAC Left 0 = Power down 1 = Power up Power Management 7 DACR 0 DAC Right 0 = Power down 1 = Power up Power Management 6 LOUT1 0 LOUT1 Output Buffer 0 = Power down 1 = Power up Power Management 5 ROUT1 0 ROUT1 Output Buffer 0 = Power down 1 = Power up Power Management 4 SPKL 0 SPK_LP/SPK_LN Output Buffers 0 = Power down 1 = Power up Power Management 3 SPKR 0 SPK_RP/SPK_RN Output Buffers 0 = Power down 1 = Power up Power Management 2 0 Reserved 1 OUT3 0 OUT3 Output Buffer 0 = Power down 1 = Power up Power Management 0 PLL_EN 0 PLL Enable 0 = Power down 1 = Power up Power Management R27 (1Bh) Additional Control (3) 8:7 00 Reserved 6 VROI 0 VREF to Analogue Output Resistance (Disabled Outputs) 0 = 500 VMID to output 1 = 20k VMID to output Enabling the Outputs 5 0 Reserved 4 0 Reserved 3 OUT3CAP 0 Capless Mode Headphone Switch Enable 0 = OUT3 unaffected by jack detect events 1 = OUT3 enabled and disabled together with HP_L and HP_R in response to jack detect events Headphone Jack Detect 2:0 ADC_ALC_SR 000 ALC Sample Rate 000 = 44.1k / 48k 001 = 32k 010 = 22.05k / 24k 011 = 16k 100 = 11.25k / 12k 101 = 8k 110 and 111 = Reserved Automatic Level Control R28 (1Ch) Anti-Pop 1 8 0 Reserved 7 POBCTRL 0 Selects the bias current source for output amplifiers and VMID buffer 0 = VMID / R bias 1 = VGS / R bias |
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