WM8960CGEFLSLASHV datasheet(11/94 Pages) CIRRUS

11 / 94 page

WM8960

Rev 4.4

Test Conditions

DCVDD = 1.8V, DBVDD = 3.3V, AVDD = SPKVDD1 = SPKVDD2 = 3.3V, TA = +25

oC, 1kHz signal, fs = 48kHz, PGA gain = 0dB,

24-bit audio data unless otherwise stated.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Speaker Supply Leakage current

ISPKVDD

SPKVDD1=SPKVDD2

=5V;

All other supplies

disconnected

SPKVDD1=SPKVDD2

=5V;

All other supplies 0V

Power Supply Rejection Ratio

(100mV ripple on

SPKVDD1/SPKVDD2 @217Hz)

PSRR

DAC to speaker playback

L/RINPUT3 to speaker

playback

Analogue Reference Levels

Midrail Reference Voltage

VMID

–3%

AVDD/2

+3%

Microphone Bias

Bias Voltage

VMICBIAS

3mA load current

MBSEL=0

–5%

0.9

AVDD

+ 5%

3mA load current

MBSEL=1

–5%

0.65

AVDD

+ 5%

Bias Current Source

IMICBIAS

Output Noise Voltage

1kHz to 20kHz

nV/

Hz

Digital Input / Output

Input HIGH Level

VIH

0.7

DBVDD

Input LOW Level

VIL

0.3

DBVDD

Output HIGH Level

VOH

IOL=1mA

0.9

DBVDD

Output LOW Level

VOL

IOH=-1mA

0.1

DBVDD

Input capacitance

Input leakage

-0.9

0.9

OUTPUT PGA GAIN

Output PGA Gains (Target gain, not measured)

-80

-70

-60

-50

-40

-30

-20

-10

100

120

140

Volume Register Setting

Figure 1 Output PGA Gains (LOUT1VOL, ROUT1VOL, SPKLVOL, SPKRVOL)

WM8960CGEFL/V Datasheet(PDF) 11 Page - Cirrus Logic

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