W6100 datasheet(40/149 Pages) WIZNET

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W6100 – Hardwired Dual TCP/IP Stack Controller

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1 : Enable Power Down Mode

SYS_CLK is automatically changed to 25MHz.

ref) 8.4.1 Reset Timing

Reserved

10BASE-Te MODE

It’s valid only in case that PHYSR[MODE2:MODE0] = ‘000’.

0 : Disable 10BASE-Te MODE

1 : Enable 10BASE-Te MODE

[2:1]

Reserved

RST

PHY Reset

On PHY HW Reset, SYS_CLK is changed to 25MHz.

When reset is completed, this bit is cleared automatically and SYS_CLK

is restored to the previous setting clock.

ref) 8.4.1 Reset Timing

0 : Normal Operation

1 : PHY HW Reset

4.1.26 NET4MR (Network IPv4 Mode Register)

[R=W] [0x4000] [0x00]

NET4MR sets special options for IPv4.

UNRB

PARP

RSTB

R=W

Bit

Symbol

Description

[7:4]

Reserved

UNRB

UDP4 Port Unreachable Packet Block

When UDP4 packet is transmitted to SOCKET that is not opened,

destination port unreachable packet is transmitted.

It can be a target of UDP port scan attack. To prevent this,

unreachable packet transmission can be blocked.

0 : Unblock

1 : Block

PARP

ARPv4 for PINGv4 Reply

Set to issue ARPv4 before PINGv4 Reply.

W6100 Datasheet(PDF) 40 Page - WIZnet Co., Ltd

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