ATM90E32AS-AU-R datasheet(20/84 Pages) ATMEL

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M90E32AS [Datasheet]

Atmel-46003B-SE-M90E32AS-Datasheet_02122015

3.7.3

FREQUENCY MONITORING RELATED STATUS AND EVENTS

The measured frequency is compared with two thresholds configured in the the FreqLoTh register and the FreqHiTh regis-

ter.

If the measured frequency goes beyond the range defined by the two thresholds, the FreqLoST bit (b11, EMMState1) and

FreqHiST bit

(b15, EMMState1) will be asserted.

The interrupt status will be updated as well; and if enabled, interrupt signal can be asserted.

3.7.4

ZERO-CROSSING DETECTION

Zero-crossing detector detects the zero-crossing point of the fundamental component of voltage and current for each of the

3 phases. Refer to 6.5 Zero-Crossing Timing.

Zero-crossing signal can be independently configured and output. Refer to the definition of the ZXConfig register.

3.7.5

NEUTRAL LINE OVERCURRENT DETECTION

The neutral line rms current (calculated) INC is checked with the threshold defined in the InWarnTh register. If the N Line

current is greater than the threshold, the INOv0ST bit (b7, EMMState0) is set. IRQ0 is generated if the INOv0IntEN bit (b7,

EMMIntEn0) is set.

3.7.6

PHASE SEQUENCE ERROR DETECTION

The phase sequence is detected in two cases: 3P4W and 3P3W, which is defined by the 3P3W bit (b8, MMode0).

3P4W case:

Correct sequence: Voltage/current zero-crossing sequence: phase-A, phase-B and phase-C.

3P3W case:

Correct sequence: Voltage/current zero-crossing between phase-A and phase-C is greater than 180 degree.

If the above mentioned criteria are violated, it is assumed as a phase sequence error, the URevWnST bit (b9, EMMState0)

or the IRevWnST bit (b9, EMMState0) will be set.

ATM90E32AS-AU-R Datasheet(PDF) 20 Page - ATMEL Corporation