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ATM90E32AS-AU-R Datasheet(PDF) 31 Page - ATMEL Corporation |
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ATM90E32AS-AU-R Datasheet(HTML) 31 Page - ATMEL Corporation |
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31 / 84 page ![]() 31 M90E32AS [DATASHEET] Atmel-46003B-SE-M90E32AS-Datasheet_02122015 Figure-17 Read Sequence Write Sequence: Figure-18 Write Sequence 4.2.2 RELIABILITY ENHANCEMENT FEATURE The SPI read/write transaction is CS-low defined. Each transaction can only access one register. Within each CS-low defined transaction: Write: access occurs only when CS goes from low to high and there are exactly 32 SCLK cycles received during CS low period. Read: if SCLK>=16 (full address received), data is read out from internal registers and gets to the SDO pin; and the LastS- PIData register is updated. The R/C registers can only be cleared after the LastSPIData register is updated. CS SCLK SDI SDO 10 1 2 3 4 5 6 7 8 9 111213141516171819202122 24 A3 A6 A5 A4 Register Address High Impedance D15 Don't care D0 16-bit data 23 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 25 26 A2 A1 A0 27 28 29 30 31 32 A8 X X X X X A7 A9 CS SCLK SDI SDO 10 1 234 5678 9 11 12 13 14 15 16 17 18 19 20 21 22 23 A3 A7 A6 A5 A4 16-bit data High Impedance D0 D7 D6 D5 D4 D3 D2 D1 Register Address D15 24 D14D13 D12D11 D10 D9 D8 A0 A1 A2 25 26 27 28 29 30 31 32 A8 X X X X X A9 |
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