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TMS320F28375DPZP Datasheet(PDF) 35 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 226 page  TERMINAL I/O/Z (1) DESCRIPTION NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO. X1 G19 123 68 I On-chip crystal-oscillator input. To use this oscillator, a quartz crystal must be connected across X1 and X2. If this pin is not used, it must be tied to GND. This pin can also be used to feed a single-ended 3.3-V level clock. In this case, X2 is a No Connect (NC). X2 J19 121 66 O On-chip crystal-oscillator output. A quartz crystal may be connected across X1 and X2. If X2 is not used, it must be left unconnected. NO CONNECT NC H4 – – No connect. BGA ball is electrically open and not connected to the die. JTAG TCK V15 81 50 I JTAG test clock with internal pullup (see Section 8.6) TDI W13 77 46 I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO W15 78 47 O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (3) TMS W14 80 49 I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST V14 79 48 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ or smaller resistor generally offers adequate protection. The value of the resistor is application-specific. TI recommends that each target board be validated for proper operation of the debugger and the application. This pin has an internal 50-ns (nominal) glitch filter. INTERNAL VOLTAGE REGULATOR CONTROL VREGENZ J18 119 64 I Internal voltage regulator enable with internal pulldown. The internal VREG is not supported and must be disabled. Connect VREGENZ to VDDIO. ANALOG, DIGITAL, AND I/O POWER www.ti.com TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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