TMS320F28375DPZP datasheet(70/226 Pages) TI

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8.9.4 Flash Parameters

The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through

128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution

from RAM. Factoring in discontinuities, most applications will run with an efficiency of approximately 80% relative

to code executing from RAM. This flash efficiency lets designers realize a 2× improvement in performance when

migrating from the previous generation of MCUs.

This device also has an OTP (One-Time-Programmable) sector used for the dual code security module (DCSM),

which cannot be erased after it is programmed.

Table 8-4 shows the minimum required flash wait states at different frequencies. Section 8.9.4.1 shows the flash

parameters.

Table 8-4. Flash Wait States

CPUCLK (MHz)

MINIMUM WAIT STATES (1)

EXTERNAL OSCILLATOR OR CRYSTAL

INTOSC1 OR INTOSC2

150 < CPUCLK ≤ 200

145 < CPUCLK ≤ 194

100 < CPUCLK ≤ 150

97 < CPUCLK ≤ 145

50 < CPUCLK ≤ 100

48 < CPUCLK ≤ 97

CPUCLK ≤ 50

CPUCLK ≤ 48

(1)

Minimum required FRDCNTL[RWAIT].

8.9.4.1 Flash Parameters

PARAMETER

MIN

TYP

MAX

UNIT

Program Time(1)

128 data bits + 16 ECC bits

300

µs

8KW sector

180

32KW sector

360

720

Erase Time(2) at < 25 cycles

8KW sector

32KW sector

Erase Time(2) at 20k cycles

8KW sector

105

4000

32KW sector

110

4000

Nwec

Write/erase cycles

20000

cycles

tretention

Data retention duration at TJ = 85°C

years

(1)

Program time is at the maximum device frequency. Program time includes overhead of the flash state machine but does not include

the time to transfer the following into RAM:

•

Code that uses flash API to program the flash

•

Flash API itself

•

Flash data to be programmed

In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for

programming. The transfer time will significantly vary depending on the speed of the JTAG debug probe used.

Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes

Program verify by the CPU. The program time does not degrade with write/erase (W/E) cycling, but the erase time does.

Erase time includes Erase verify by the CPU and does not involve any data transfer.

(2)

Erase time includes Erase verify by the CPU.

Note

The Main Array flash programming must be aligned to 64-bit address boundaries and each 64-bit

word may only be programmed once per write/erase cycle. For more details, see the "Flash: Minimum

Programming Word Size" advisory in the TMS320F2837xD Dual-Core MCUs Silicon Errata .

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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TMS320F28375DPZP Datasheet(PDF) 70 Page - Texas Instruments

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