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TMS320F28375DPZP Datasheet(PDF) 48 Page - Texas Instruments |
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TMS320F28375DPZP Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 226 page  7.5 Connections for Unused Pins For applications that do not need to use all functions of the device, Table 7-6 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 7-6, any are acceptable. Pins not listed in Table 7-6 must be connected according to Section 7.2.1. Table 7-6. Connections for Unused Pins SIGNAL NAME ACCEPTABLE PRACTICE Analog VREFHIx Tie to VDDA VREFLOx Tie to VSSA ADCINx • No Connect • Tie to VSSA Digital GPIOx • No connection (input mode with internal pullup enabled) • No connection (output mode with internal pullup disabled) • Pullup or pulldown resistor (any value resistor, input mode, and with internal pullup disabled) X1 Tie to VSS X2 No Connect TCK • No Connect • Pullup resistor TDI • No Connect • Pullup resistor TDO No Connect TMS No Connect TRST Pulldown resistor (2.2 kΩ or smaller) VREGENZ Tie to VDDIO. VREG is not supported. ERRORSTS No Connect FLT1 No Connect FLT2 No Connect Power and Ground VDD All VDD pins must be connected per Section 7.2.1. VDDA If a dedicated analog supply is not used, tie to VDDIO. VDDIO All VDDIO pins must be connected per Section 7.2.1. VDD3VFL Must be tied to VDDIO VDDOSC Must be tied to VDDIO VSS All VSS pins must be connected to board ground. VSSA If a dedicated analog ground is not used, tie to VSS. VSSOSC If an external crystal is not used, this pin may be connected to the board ground. TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021 www.ti.com 48 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: TMS320F28379D TMS320F28379D-Q1 TMS320F28378D TMS320F28377D TMS320F28377D-Q1 TMS320F28376D TMS320F28375D TMS320F28374D |
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