TMS320F28375DPZP datasheet(17/226 Pages) TI

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7.2 Signal Descriptions

Section 7.2.1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The

peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be

available in all devices. See Table 6-1 for details. All GPIO pins are I/O/Z and have an internal pullup, which can

be selectively enabled or disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups are

not enabled at reset.

7.2.1 Signal Descriptions

TERMINAL

I/O/Z

(1)

DESCRIPTION

NAME

MUX

POSITION

ZWT

BALL

NO.

PTP

NO.

PZP

NO.

ADC, DAC, AND COMPARATOR SIGNALS

VREFHIA

ADC-A high reference. This voltage must be driven into

the pin from external circuitry. Place at least a 1-µF

capacitor on this pin for the 12-bit mode, or at least a 22-

µF capacitor for the 16-bit mode. This capacitor should be

placed as close to the device as possible between the

VREFHIA and VREFLOA pins.

NOTE: Do not load this pin externally.

VREFHIB

ADC-B high reference. This voltage must be driven into

the pin from external circuitry. Place at least a 1-µF

capacitor on this pin for the 12-bit mode, or at least a 22-

µF capacitor for the 16-bit mode. This capacitor should be

placed as close to the device as possible between the

VREFHIB and VREFLOB pins.

NOTE: Do not load this pin externally.

VREFHIC

–

ADC-C high reference. This voltage must be driven into

the pin from external circuitry. Place at least a 1-µF

capacitor on this pin for the 12-bit mode, or at least a 22-

µF capacitor for the 16-bit mode. This capacitor should be

placed as close to the device as possible between the

VREFHIC and VREFLOC pins.

NOTE: Do not load this pin externally.

VREFHID

–

ADC-D high reference. This voltage must be driven into

the pin from external circuitry. Place at least a 1-µF

capacitor on this pin for the 12-bit mode, or at least a 22-

µF capacitor for the 16-bit mode. This capacitor should be

placed as close to the device as possible between the

VREFHID and VREFLOD pins.

NOTE: Do not load this pin externally.

VREFLOA

ADC-A low reference.

On the PZP package, pin 17 is double-bonded to VSSA

and VREFLOA. On the PZP package, pin 17 must be

connected to VSSA on the system board.

VREFLOB

ADC-B low reference

VREFLOC

–

ADC-C low reference

VREFLOD

–

ADC-D low reference

ADCIN14

Input 14 to all ADCs. This pin can be used as a general-

purpose ADCIN pin or it can be used to calibrate all ADCs

together (either single-ended or differential) from an

external reference.

CMPIN4P

Comparator 4 positive input

ADCIN15

Input 15 to all ADCs. This pin can be used as a general-

purpose ADCIN pin or it can be used to calibrate all ADCs

together (either single-ended or differential) from an

external reference.

CMPIN4N

Comparator 4 negative input

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TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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TMS320F28375DPZP Datasheet(PDF) 17 Page - Texas Instruments

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