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LTM4686 Datasheet(PDF) 9 Page - Analog Devices

Part # LTM4686
Description  Quad 31.25A or Single 125A 關Module Regulator with Digital Power System Management
PDF  132 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4686 Datasheet(HTML) 9 Page - Analog Devices

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LTM4681
9
Rev. 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the specified internal
operating temperature range (Note 2). Specified as each individual output channel (Note 4). TA = 25°C, VIN = 12V, RUNn = 3.3V,
RUNP = 0, FREQUENCY_SWITCH = 350kHz and VOUTn commanded to 1.000V unless otherwise noted. Configured with factory-default
EEPROM settings and per Test Circuit 1, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SVIN_THR
VSVIN_nn Threshold to Enable VBIAS
Switchover
SVIN_nn Rising
7
7.5
V
SVIN_THF
VSVIN_nn Threshold to Disable VBIAS
Switchover
SVIN_nn Falling
6.5
V
VDD33_nn Regulator
VVDD33nn
Internal VDD33 Voltage
4.5V < VINTVCC_nn
3.2
3.3
3.4
V
ILIM
VDD33 Current Limit
VDD33_nn = GND, VIN_nn = INTVCC_nn = 4.5V
100
mA
VVDD33_OV
VDD33 Overvoltage Threshold
3.5
V
VVDD33_UV
VDD33 Undervoltage Threshold
3.1
V
VDD25_nn Regulator
VVDD25nn
Internal VDD25 Voltage
2.5
V
ILIM
VDD25 Current Limit
VDD25_nn = GND, VIN_nn = INTVCC_nn = 4.5V
80
mA
Oscillator and Phase-Locked Loop (PLL)
fRANGE
PLL SYNC Range
Synchronized with Falling Edge of SYNC
l
250
1000
kHz
fOSC
Oscillator Frequency Accuracy
Frequency Switch = 250kHz to 1000kHz (Note 15)
l
±7.5
%
VTH(SYNC_nn)
SYNC Input Threshold
VSYNC Falling
VSYNC Rising
1
1.5
V
V
VOL(SYNC_nn)
SYNC Low Output Voltage
ILOAD = 3mA
0.2
0.4
V
ILEAK(SYNC_nn)
SYNC Leakage Current in Slave Mode 0V ≤ VPIN ≤ 3.6V
±5
µA
θSYNC-θ0,-θ2
SYNC to Ch0, Ch2 Phase
Relationship Based on the Falling
Edge of Sync and Rising Edge of
SW0, SW2
MFR_PWM_CONFIG[2:0] = 0,2,3
MFR_PWM_CONFIG[2:0] = 5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0]= 4,6
0
60
90
120
Deg
Deg
Deg
Deg
θSYNC-θ1,-θ3
SYNC to Ch1, Ch3 Phase
Relationship Based on the Falling
Edge of Sync and Rising Edge of
SW1, SW3
MFR_PWM_CONFIG[2:0] = 3
MFR_PWM_CONFIG[2:0] = 0
MFR_PWM_CONFIG[2:0] = 2,4,5
MFR_PWM_CONFIG[2:0] = 1
MFR_PWM_CONFIG[2:0] = 6
120
180
240
270
300
Deg
Deg
Deg
Deg
Deg
EEPROM Characteristics
Endurance
(Note 13)
0°C ≤ TJ ≤ 85°C During EEPROM Write Operations
l
10,000
Cycles
Retention
(Note 13)
TJ < 125°C
l
10
Years
Mass_Write
Mass Write Operation Time
STORE_USER_ALL, 0°C < TJ < 85°C
During EEPROM Write Operation
440
4100
ms
Leakage Current SDA_nn, SCL_nn, ALERT_nn, RUNn
IOL
Input Leakage Current
OV ≤ VPIN ≤ 5.5V
l
±5
µA
Leakage Current FAULTn, PGOODn
IGL
Input Leakage Current
OV ≤ VPIN ≤ 3.6V
l
±2
µA
Digital Inputs SCL_nn, SDA_nn, RUNn
VIH
Input High Threshold Voltage
l
1.35
V
VIL
Input Low Threshold Voltage
l
0.8
V
VHYST
Input Hysteresis
SCL, SDA
0.08
V
CPIN
Input Capacitance
10
pF



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