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EMC1702 Datasheet(PDF) 38 Page - Microchip Technology

Part # EMC1702
Description  High-Side Current-Sense and Dual 1째C Temperature Monitor
PDF  60 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

EMC1702 Datasheet(HTML) 38 Page - Microchip Technology

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EMC1702
DS20006455A
38
2020 Microchip Technology Inc.
5.9
Tcrit Limit Registers
The Tcrit Limit Registers are used to determine whether a critical thermal event has occurred. If the
measured temperature meets or exceeds the Tcrit Limit, the THERM pin is asserted.
Unlike the ALERT pin, the THERM pin cannot be masked. Additionally, the THERM pin will be released
once the temperature drops below the corresponding threshold minus the Tcrit Hysteresis.
5.10 External Diode Fault Register
The External Diode Fault Register indicates that External Diode 1 caused the FAULT bit in the Status
Register to be set. This register is cleared when it is read.
Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault.
5.11 Channel Mask Register
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads a diode fault or out-of-limit error. The
channel mask does not mask the THERM pin.
Bit 7 - VSENSE_MASK - Masks the ALERT pin from asserting when the VSENSE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
‘0’ (default) - The VSENSE voltage channel will cause the ALERT pin to be asserted (if enabled).
Table 5.10 Tcrit Limit Registers
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
19h
R/W
External
Diode 1 Tcrit
Limit
Sign
64
32
16
8
4
2
1
64h
(100°C)
20h
R/W
Internal Diode
Tcrit Limit
Sign
64
32
16
8
4
2
1
64h
(100°C)
21h
R/W
Tcrit
Hysteresis
-
64
32
16
8
4
2
1
0Ah
(10°C)
Table 5.11 External Diode Fault Register
ADDR.
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Bh
R-C
External
Diode Fault
-
-
-
-
-
-
E1FLT
-
00h
Table 5.12 Channel Mask Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
1Fh
R/W
Channel
Mask
VSENSE_
MASK
VSRC_
MASK
PEAK_
MASK
-
-
-
E1
MASK
INT
MASK
00h



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