PIMXRT516SCVM2A datasheet(20/128 Pages) NXP

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i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021

NXP Semiconductors

Modules list

3.1

Special signal considerations

Table 4 lists special signal considerations for the i.MX RT1170 processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, Package information and contact

assignments.” Signal descriptions are provided in the i.MX RT1170 Reference Manual

(IMXRT1170RM).

WDOG1

WDOG2

WDOG3

WDOG4

Watch Dog

Timer Peripherals

WDOG1 and WDOG2 Timer support two comparison

points during each counting period. Each of the

comparison points is configurable to evoke an interrupt

to the Arm core, and a second point evokes an external

event on the WDOG line.

WDOG3 and WDOG4 modules are high reliability

independent timers that are available for system to use.

They provide a safety feature to ensure software is

executing as planned and the CPU is not stuck in an

infinite loop or executing unintended code. If the WDOG

module is not serviced (refreshed) within a certain

period, it resets the MCU. Windowed refresh mode is

supported as well.

XBARA

XBARB

Cross BAR

Cross Trigger

Each crossbar switch is an array of muxes with shared

inputs. Each mux output provides one output of the

crossbar. The number of inputs and the number of

muxes/outputs are user configurable and registers are

provided to select which of the shared inputs are routed

to each output.

XECC

External ECC Controller

Memories and

Memory Controllers

XECC can be used as a gasket module on AXI bus to

support ECC function for external memory.

XRDC

Extended Resource

Domain Controller

Security

The XRDC provides an integrated, scalable

architectural framework for access control, system

memory protection, and peripheral isolation. It allows

software to assign chip resources including processor

cores, non-core bus masters, memory regions, and

slave peripherals to processing domains to support

enforcement of robust operational environments.

Table 4. Special signal considerations

Signal Name

Remarks

CLK1_P/ CLK1_N

This differential output is reserved for NXP internal use. For users, this output must be a no

connect.

DCDC_PSWITCH

PAD is in DCDC_IN domain and connected to ground to bypass DCDC.

To enable DCDC function, assert DCDC_PSWITCH with at least 1 ms delay after the DCDC_IN

rising edge.

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

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