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PIMXRT516SCVM2A Datasheet(PDF) 74 Page - NXP Semiconductors

Part # PIMXRT516SCVM2A
Description  i.MX RT1170 Crossover Processors Data Sheet for Consumer Products
PDF  128 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PIMXRT516SCVM2A Datasheet(HTML) 74 Page - NXP Semiconductors

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i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 1, 05/2021
74
NXP Semiconductors
Electrical characteristics
4.6.3
LCD Controller timing parameters
Figure 30 shows the LCD timing and Table 71 lists the timing parameters.
Figure 30. LCD timing
4.7
Audio
This section provides information about SAI/I2S.
4.7.1
SAI/I2S switching specifications
This section provides the AC timings for the SAI in master (clocks driven) and slave (clocks input) modes.
All timings are given for non-inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]
= 0) and non-inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock
and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal
(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.
Table 71. LCD timing parameters
ID
Parameter
Symbol
Min
Max
Unit
L1
LCD pixel clock frequency
tCLK(LCD)
—
75/1501
1 For eLCDIF or LCDIFv2, the maximum pixel clock frequency of parallel IO interface is 75 MHz, while it is 150 MHz for MIPI
DSI interface.
MHz
L2
LCD pixel clock high (falling edge capture)
tCLKH(LCD)
3
—
ns
L3
LCD pixel clock low (rising edge capture)
tCLKL(LCD)
3
—
ns
L4
LCD pixel clock high to data valid (falling edge capture)
td(CLKH-DV)
-1
1
ns
L5
LCD pixel clock low to data valid (rising edge capture)
td(CLKL-DV)
-1
1
ns
L6
LCD pixel clock high to control signal valid (falling edge capture)
td(CLKH-CTRLV)
-1
1
ns
L7
LCD pixel clock low to control signal valid (rising edge capture)
td(CLKL-CTRLV)
-1
1
ns
L1
L2
L3
L4
LCDn_CLK
(falling edge capture)
LCDn_CLK
(rising edge capture)
LCDn_DATA[23:00]
LCDn Control Signals
L5
L6
L7



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